Simple Combinatorial Programmable Logic Devices

Simple Combinatorial Programmable Logic Devices

The Basic Version Of The PAL This basic type shown in figure 18.8 is directly derived from the PROM.

The component offers 10 inputs and 8 outputs which are active high (Active High – H). These three characteristics are responsible for the additional name 10H8. The 10 inputs feed in true and inverted mode the vertical input lines which are crossing the horizontal AND lines. This is the programmable AND matrix. Thus any of the 16 AND lines disposes of 20 physical inputs; however, only a maximum of 10 inputs can be used. Otherwise a true signal and an inverted signal would be conjunctively linked together, which always results in the low value. The 16 AND lines are combined in pairs with OR gates feeding the 8 output signals. A compact form of all information about the device is also included in the functional block diagram as shown in figure 18.7.

The possibilities offered by the PAL 10H8 are illustrated by means of three examples. In a microprocessor system an enable signal f for a port has to be produced with respect to a given address

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The binary representation of the address provides the logic operation of the 10 address bits.

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This wide AND operation is ‘programmed’ at pin 19 in fig. 18.8: those programmable memory cells which are marked by an ‘x’ in the upper AND term remain intact, all others will be destroyed during the programming process. The second AND term of pin 19 is not needed, it must always supply a ‘low’. For this purpose, all programmable memory cells remain intact. An address decoder realized in this way generates the intended enable signal within typical 0.5 ns.

In addition to this, 4 event lines have to be monitored and flagged with graded priority in the same microprocessor system. In table 18.2 the status signals are allocated to the events, respectively.

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In figure 18.8 the ‘programming’ is carried out at pin 15 and pin 14. In addition, the outputs of pin 13 (g) and pin 12 (h) with the inputs of pin 8 and pin 11 have to be connected externally. This results in a cascaded AND-OR operation. The component is used twice and the delay is doubled. For the 1-bit full adder a component with at least 4 AND terms per OR gate is of course more suitable.

Additional Internal Feedback and Switchable Output Drivers

The logic diagram of PAL 10H8 in fig. 18.8 is already complex enough. In order to concentrate on the essential issue, the following sections deal with simple examples. However, the indications given follow the real models which are shown in brackets.

The example of the full adder shows that a cascade of AND-OR logic is sometimes necessary. For this purpose, some PALs are provided with an internal feedback as shown in fig. 18.9.

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In addition to this, a controllable output driver inverts the signal of the OR gate. Thus the output becomes low active (active low – L) which leads to the ‘L’ in the suffix of PAL 4L2 (of PAL 16L8). The upper AND term with the abbreviation of OE (output enable) serves as a control of the output driver. Three different connection types can be programmed in this way.

a) OE = 1: all programmable memory cells are destroyed, the pull-up resistor is active: The output driver is constantly enabled and the con- nection works as an output.

b) OE = 0: all programmable memory cells are intact, true signals and inverted signals result in low: The output driver is constantly disabled and therefore highly resistive. The connection can now be used as an additional input.

c) OE is changed by the logic operation while operating. In this case the connection operates in both directions as input/output.

The internal feedback allows the immediate pro- gramming of an output signal in the AND matrix. If it is used in adjacent AND terms, there will be a multi-stage ‘transparent’ logic. If the output signal is, however, used in its own AND terms, there will be a feedback. Two possibilities have to be distinguished:

There will be a positive feedback if the re-feeding driver/inverter relinquishes the inversion of the output driver. This is programmed in the upper half

of fig. 18.9. As long as pin 5 indicates ‘low’, the positive feedback term supplies a ‘high’. However, if pin 5 becomes ‘high’ it will be confirmed by a ‘low‘ of the positive feedback term and will be maintained until the voltage is cut off. Such a circuit catches the high.

There will be an inverse feedback if the inversion is maintained in the feedback. As shown in the lower part of fig. 18.9, the programmed circuit is never satisfied and constantly changes the output value at pin 4. There is a ring oscillator which could be switched on and off via the middle AND term. It should actually be handled with caution, as it does not have any guaranteed frequency.

The ring oscillator may be useful for test purposes. The delay time of the complete feedback loop, e.g., of the input driver/inverter, the AND line, the OR gate, and the output driver occurs between two counter-sense clock edges. This is identical with the gate sequence of an input pin to an output pin. Thus the delay time tPD between the pins can be determined by the measured oscillator frequency f .

Programmable Polarity

The two PALs dealt with above both have a defined output polarity, either active high or active low. An additional exclusive OR (EXOR) placed before each output allows the individual programming of the polarity. Figure 18.10 shows an EXOR gate with a programmable input.

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In the case of an in tact programmable memory cell the input p shows ‘low’, and in case of a destroyed fusible link there will be ‘high’ by means of pull up. As shown in the truth table 18.4, the output a for p = 0 is identical with the input e. For p = 1, however, ‘e’ will be inverted to become ‘a’.

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The possibility of inverting may be very helpful. A code transcriber from BCD Code (Binary Coded Decimal) to the Excess 3 Gray Code according to table 18.5 is to be realized by means of the PAL 4P4 (of PAL 10P8).

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The position g2 needs too many AND terms, so the code transcriber seems to be too much for the PAL 4P4. Using the programmable inverter it is however possible to alternatively program the inverter function. It needs one AND term only. The four equations can now all be programmed into PAL 4P4 as shown in fig. 18.11.

Apart from selecting between 1 active (H) and 0 active (L), the programmable inverter also allows one to reduce the AND terms required in this example.

Random Multiple Allocation of AND Terms

The examples of the full adder and the code transcriber demonstrate that there may be a short of definitely allocated AND terms. It would be more favorable to have a more flexible distribution among the outputs. With the OR matrix, which is also programmable, such a possibility is presented by the PLA (Programmable Logic Array) structure shown in fig. 18.12. By means of the OR line any number of the existing AND terms may be allocated to any output (Product Term Sharing).

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This is to be demonstrated with the example of the full adder. The equations to be programmed are as follows in the original Sum of Products

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Transformation is no longer necessary, then the PLA is configured in a way which is adapted to the respective problem. Output 7 is assigned to four AND terms and output 6 to three.

Distributed in this way, the two equations can be programmed directly, as shown in fig. 18.12.

The easy use and the flexibility of the PLA is not for nothing. The programmable OR matrix requires more silicon space than defined OR gates. Simple PAL components are therefore available at a lower price.

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