Digital Simulation:Verification of Testability with Simulation

Verification of Testability with Simulation

Theory of fault simulation is explained in detail in chapter 15. In the following the performance of simulation tools is demonstrated with design examples.

Results of fault simulation will give answers to the following questions:

• How effective are the test stimuli (test vectors) used?

• What about the testability of the design?

For fault simulation the software Quickfault of Mentor Graphics was used. The design examples are parts of an IC which was implemented at IMS (Institut für Mikroelektronik Stuttgart) in an 0.8 μ process.

For economic reasons in fault simulation mainly simple stuck at 1 and stuck at 0 faults are used in simulation. But what about the ability of detecting faults for a given design in a given technology? In practice it is a good approach to use these two models. Up to now there is still no conclusive explanation for this effect.

Fault coverage is a term for giving the percentage of the number of faults defined by the designer which are detected with the applied test stimuli. This is an example of fault coverage which shows that one must read the specifications thoroughly to rate a statement concerning fault coverage: For fault simulation the designer decides to insert only s.a.1 faults in 100 out of 120 nodes in his circuit. After fault simulation 95 faults are detected. The fault coverage is 95 % because only the inserted

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faults are considered. The number 95 does obviously not refer to s.a.0 faults which have not been simulated!

To estimate the fault coverage of a design it must be checked at how many nodes and which faults have been inserted.

Design Example: Decoder for a Seven Segment Display

Combinatorial logic parts in a system should be arranged in a way that all possible combinations of inputs may be applied. For such parts 100 % fault coverage is desirable. A seven segment decoder is a good example of such a circuit module.

Logic function of a seven segment decoder

A seven segment decoder is a combinational logic circuit with 4 inputs and 7 outputs to drive 7 segments of a display (fig. 11.31).

In order to detect faults test stimuli must be de- signed in such a way that at least each single node of the circuit will change once from 0 to 1 during simulation. Additionally the faulty response of the circuit must be recognized at least at one primary output.

In order to show different considerations of fault simulation and fault detection, at first test stimuli are developed which are not yet optimal. They will be improved in a second step.

Fault simulation with incomplete test stimuli

The circuit has 7 outputs sega, segb, segc, segd, sege, segf, segg and 4 inputs d3, ... , d0. For each step of simulation one test vector is defined. In list 11.6 the test vector is called db. One combination of a binary word with 4 bit (d3, ..., d0) will be assigned to a test vector. In this case, input d3 was deliberately not activated in order to show the effect in fault simulation.

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Unfortunately software vendors have no standard definitions which describe different kinds of faults. Therefore the terms used in Quickfault will be explained briefly in table 11.7.

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After fault simulation all undetected faults can be displayed graphically in the schematic (fig. 11.35) directly at the elements concerned. The designer may think about the reasons why a fault was not detected and change test vectors accordingly. It is shown in fig. 11.35 that undetected faults are at elements which are connected to input d3.

Fault simulation with augmented test stimuli

As a second step input d3 will be included in the test stimuli (list 11.8). All 16 combinations of 4 inputs are applied to the circuit.

The log of the fault simulator (list 11.9) shows fault coverage of 100 %.

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List 11.9 Part of the log of fault simulation with 16 test vectors: Fault 100 %

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Another interesting question is: how many faults are detected at which test vector? This information is displayed in a histogram (fig. 11.36). It shows the effectiveness of each test vector. In fig. 11.36 two faults are detected in test cycle 14 and 15 which is indicated by a small line. At test cycle 16 nothing is detected. Test vector 16 is obsolete and it could be removed.

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