Printed Circuit Board Design:PCB Layout

PCB Layout

PCB Layout Overview

Netlist generation: From the schematic the netlist is generated by the EDA software. Layout means the placement of all components listed in the netlist and the routing of all electrical interconnection in defined layers between the pins of the components as described by the nets in the netlist.

Figure 25.9 shows the layout design flow.

Project library generation: In many cases there are components with the same electrical characteristics, but mounted in different packages. Figures 25.6 and 25.7 show examples, in which the same type of operational amplifier is available in a DIL package or in a TO5 package. For the layout process the user must therefore select first a suitable package. Thus the logic symbols of the components must be assigned to the packages by defining the part number. This is done by choosing the available part numbers from a library for a given device. If there is no part of this type available in the library, the user has to create a new symbol or modify an existent one. In the same way packages may also be newly created or mapping files edited. All selected and prepared objects are collected in a project specific library, where they are maintained and made available for the next process steps.

Placement of components: Placement is a very important step. Although it might be done automatically, most components are still placed inter- actively. There are many considerations made in finding the best placement, which are difficult to implement in software tools or are not available in the formal specification of the board. Such considerations are the geometric arrangement of the connectors, size of the components, but also density of the interconnections, soldering constraints, directional requirements, etc. Bad placement leads to un-routable boards or to more interconnection layers than intended. Manual placement is sup- ported in modern tools by many aids, so the term interactive placement is mostly used. In section 25.4.5 the placement process is described more in detail.

Routing of nets: The layers on the board are routed interactively or automatically with the autorouter. Routing is possible whenever there is a valid complete placement of all components on the board. The tool, as well as the user, have to pay attention to the design rules. Design rules control several aspects of both interactive and automatic routing, such as minimum clearances between con- ductive wires and how the routers use the various pin and via pad stacks. An optimal routing grid must be specified, too. The grid should be fine enough to allow traces between ‘through hole’ pins, SMD pads, connector pads, and discretes. Without analyzing the variety of component pin pitches in the design, a grid might be chosen which works well for one type, but prevents routing be- ween pins on another component type.

In postprocessing after routing the artwork data and the manufacturing documentation are generated. This is described in section 25.4.8.

Design Rules for Printed Circuit Boards

The definition of design rules is a precondition for a reliable manufacturing of PCBs with high yield. They have to be defined carefully before the layout process starts. They are mostly influenced by the manufacturing process and in this way the board manufacturer has to deliver the required in- formation. The minimum manufacturable spacing between traces is one of the most important rules of this kind.

Design rule values control the routing process and form the basis of checking the connections created by the router. Design rules include rules for board geometry, such as the boundaries within which routing is allowed.

Design rules can be divided into the categories:

• logical layer rules;

• placement rules;

• physical layer rules;

• clearances and spacing (component spacing, pad stack drill, and component pin);

• via rules for usage of via and via spacing;

• pin rules for using of pads, direction and spacing;

• net rules for routings and interconnection, wire size and wire spacing, bends;

• package rules for board mounting.

The EDA system derives default board level and layer level routing design rules from attributes of the board geometry, such as the number of routing layers and routing directions. For the different lay- out tools specific design rules have to be defined. Placement rules will be described in section 25.4.5 and routing rules in section 25.4.8.

Professional EDA tools check the violation of the design rules during the routing process. In the case of a violation of rules an error is reported, the execution of an incorrect action is refused, and the layout process stopped. For control of consistency and quality, at every phase of the layout flow a DRC run (Design Rule Check) can be performed.

Defining Routing Grid

The user has to specify grid spacing for the

• placement of the components (placement grid); and for

• routing in each layer (routing grid).

If necessary different grids for placement and for routing may be defined. It must be noted that the choice of the grid spacing has a strong influence on the routing process. The goal is a grid that allows as many traces as possible between pads with no clearance violations. It must be noted that in general, when a uniform grid is chosen, the router needs more time to complete a pass as the grid becomes finer. For example, an 0.010 inch grid is four times as complex as an 0.020 inch grid. Usually the grid is chosen for the whole board. In some cases it might be advantageous to work with different grid spacing on the board or layer. To find the optimal grid all components used have to be evaluated for their pin pitch and pad sizes.

Figure 25.10 demonstrates the influence of the grid spacing on the traces. In figure 25.10a) a 20 mil grid was chosen, in figure 25.10b a 25 mil grid, showing that the finer grid is not better in each case. In this example the chosen trace width is 10 mil with 100 mil pitch of the 60 mil pads. The minimum clearance between the edge of the pad and the edge of the nearest trace must be 10 mil in this manufacturing process example. In figure 25.10a) it is shown that the autorouter cannot route any trace between the 60 mil pads, because the minimum distance is only 5 mils. The minimum space must be 10 mils, however. In figure 25.10b)

with a 25 mil grid the minimum space is now 15 mils. Thus a routed trace between the 60 mil pads is DRC conformant.

The example demonstrates the importance of a good choice of grid spacing on routing results.

Defining Board Geometry

The board geometry object defines the basic shape of the board. The object properties contain the values for the design rules assigned to the board. A placement of components is only allowed if the so-called board outline is defined. The board ge- ometry requires three graphically defined entities:

• the board outline;

• the board placement outline;

• the board routing outline.

The board outline represents the shape and size of the board and describes the total physical area of the board. The board placement outline defines the area where components may be placed. There should be no components placed outside this line. The board routing outline identifies the area where traces may be routed.

Some of the design rules assigned to the board add more graphical objects to the board, such as the shapes of the placement area and of the routing area. Outlines have to be specified for each side of the board and may be specified for each layer. There may be more graphical shapes for special areas, where individual rules are valid or only special actions allowed. For instance, a placement rule area defines a region on the board and specifies a component height constraint to that area. Or an  area may be specified as the placement region for a particular circuit.

Figure 25.11 shows a board with the three outlines. There is a slot defined inside the board. This could be a milling area to fit a special application

Placement of Components

The purpose of placement is to define positions for components on the board’s surface. Modern EDA systems provide both interactive and automatic placement capabilities, as well as placement sup- port features to help the user for achieving the intended results.

Interactive and automatic placement has to con- form to a set of placement rules to ensure that  components are placed in the proper areas of the board and that they are not located too close to each other. These rules are a combination of placement restrictions defined for the board geometry and placement constraints of the used component geometries.

When a board geometry is created attributes for the placement rules have to be assigned. These attributes define the following data set:

• Placement grid definition;

• Placement outline shapes; allowed;

• Placement regions where only components with certain maximum height are allowed;

• Placement region of components belonging to a predefined group;

• Placement region for components not belonging to predefined groups;

• Minimum spacing between components (fig. 25.12);

• Regions for valid component orientation (fig. 25.13).

The placement grid may differ from the routing grid. When the grids are different the user has to define the grids in such a way that some, or all, of its points coincide with each other.

Placement keep outs are optional areas within the placement area in which components cannot be validly placed. A keep out area can be associated with both top and bottom placement layers, or with only one single placement layer.

A board may contain one or more placement regions that restrict placement in those areas because of component height. Component height is defined by optional attributes assigned to individual component geometries.

Placement clearance is the value of minimum distance allowed between placed components. The component placement outline defines the space, the component needs on the board. As shown in fig. 25.12, this clearance value is used during DRC checking to prohibit placing components too close of each other. Components may be placed closer when automatic checking is switched off. In this case, clearance violations are noted in DRC, but overlapping components are reported as errors.

When a component placement outline is created for library components one or more placement out- lines can be defined. The outline may be defined for display on all placement layers, or different outlines may be defined for different placement layers. Generally the entire region defined by the component placement outline should be within the board’s placement outline. However, when the component is interactively placed its placement outline may overlap the board’s outline and still be a valid placement, as long as all the pins are within the board’s placement outline.

Generally it should be noted that a good placement is most important for the following routing process. The placement step needs in many cases most of the time effort of a PCB design. In the planning phase of board design the user must consider the criteria which should be applied to the placement. Such criteria may be to minimize net lengths, to group analog and digital circuit parts, power supply nets, etc.

Defining component orientation may be useful too. By default, a board geometry allows component placement at any orientation or angle. Directional placement orientation can be restricted to orthogonal or orthogonal and diagonal by the presence of optional board property values. This allows some regularity for similar components. In the exam- ple of fig. 25.13 it is shown that the component  columns are arranged with uneven spacing. The designer anticipates a vertical routing problem on the board and leaves space between the component columns for vertical tracks.

Individual components, a component group, or all components can be protected. Protected components cannot be moved in subsequent placement operations such as placing, moving, pivoting, rotating, etc.

An important criterion for acquisition of EDA soft- ware for the PCB design can be that of whether design variants are available. Design variants are PCBs with the same routing but different components placed, e.g., modified versions for different applications. In variants several netlists share one board. The designer places and routes all components of all variants. Some components are common to all variants, other components belong only to a distinct variant. If two or more components never appear in the same variant, the EDA system considers these components as mutually exclusive. To use this feature the related foot- print properties are added to mutually exclusive components. Mutually exclusive components can be placed in an overlapping configuration which otherwise would cause placement violation errors. Later, when generating manufacturing output, an assembly drawing and a bill of materials for a single variant are created.

Interactive Placement

Interactive placement procedures allow the de- signer to place components where he wants to place them. Automatic rule checking in the back-ground prevents invalid placement, e.g., overlap- ping of footprints, grid violations, directional orientation, outline overlapping, etc. The electrical interconnections are displayed in the form of so called overflows, which behave like rubber bands, showing which pins are connected by the same net. The designer now picks and places each component, arranged by the EDA tool in the be- ginning outside the board, until all components are validly placed on the board. The overflows are restructured with each placement. The overflow density may be displayed in a colour area coding, helping to estimate routing success. Placed components can be edited, moved, reoriented, or unplaced again interactively. During this pick and place process the full experience of the designer is used to find the optimal arrangement of the components. There are a lot of frame conditions in board design which are not captured in rules or are difficult to formulate in rules. Separation of power supply components, shielding, grouping of analog and digital circuits, etc. are examples, as well as positioning of connectors, grouping of components with same height, etc.

Figure 25.14 shows an example of an interactively placed PCB, the main IC connector is placed near the middle of the board, power supply connectors are placed in a group at the board edge, etc.

Interactive placement can be effectively combined with automatic placement, when first all critical components are place manually, then protected and then all remaining noncritical components are placed automatically. After some re-editing of placement this allows fast and effective designs and is mostly adapted.

Automatic Placement

In automatic placement the components are placed according to placement algorithms. The EDA tool finds an optimal placement in the sense of the available rules, predefined criteria, routing density, connectivity, and geometric placement conditions. One of the main criteria is to minimize the sum of all net lengths. To find this minimum several iteration steps are calculated and all the known algorithms for placement are applied. But in contrast to standard cell placement, in which the variance of cell sizes is very restricted and these algorithms

are very effective, PCB boards show very different component footprints and are difficult to handle. There are many constraints which are difficult to formulate as a rule, and because of this are not available for the optimisation process.

Figure 25.15 shows the example of fig. 25.14 now placed automatically. It is obvious that this placement is far from optimal because the e.g. connectors for power supply are distributed over the board.

Automatic placement in EDA systems supports placement on both the top and bottom layers of the board. The placement can be built gradually or all at once.

In practice, automatic placement of all components is seldom used. The usual way is to place all critical components interactively, protecting them, and then to use automatic placement for the rest. Adding components to groups by using group properties, e.g., grouping analog components to the group analog and digital components to the group digital, supports the placement process significantly.

The placement can be improved by using automatic component swapping to adjust results of automatic placement. There are several tools for re-editing and improving a valid placement inter- actively. All these tools rearrange placed components and optimise net connections. Placement may be fixed, as it is needed, e.g., for connectors, or movable which allows small movement (a few grid steps) and re-arrangement during the routing process.

Routing

Routing tools create a set of traces which connect the component pins on the board. EDA tools allow the user to route traces interactively, automatically, or both. Routing is not possible until all components are validly placed.

Routing layers can be differentiated into power layers and signal layers. Power layers contain a power and/or ground net that connects components to power and/or ground. Signal layers contain the traces that interconnect the signal pins of the components. Plated through hole vias, as well as additive technology based vias, are supported to feed routing from layer to layer. Power net and ground net can also be routed as signals on signal layers.

Routing is done in a grid of potential trace paths that run horizontally or vertically across the board (grid routing). Gridless routing is only allowed for special purposes and should be avoided. The user has to specify the grid settings for the design when he sets up the routing rules. The preferred routing direction, vertically or horizontally, is specified in a direction property belonging to the layer.

Just as placement is constrained within a defined area and by varous placement rules, a series of design rules prohibit routing on certain areas of the board (keep out areas) and maintain minimum clearances between all traces.

The basis for the routing process is again the netlist which contains all connections between component terminals. These un-routed connections are displayed as overflows or guides in a predefined colour, easily to distinguish from traces. These guides are replaced with traces as routing proceeds.

The board routing outline (fig. 25.11) limits the area within which traces can be routed. The board routing outline is the same for all routing layers. Inside the routing outline are optional keep out areas where routing traces are not allowed, either on a specific layer or on all routing layers. A routing keep out area restricts traces and vias, as a trace keep out area restricts only traces, and as a via keep out area restricts just vias. The routing outline and keep out areas are attributes of the board geometry. Keep outs can also be included in the component specification as part of the geometry definition.

Keep outs may be applied to critical nets in analog circuits, for example. An optimal routed layer improves electromagnetic interference (EMI).

Design rules control several aspects of both inter- active and automatic routing, such as the minimum clearances between traces and how the router uses the various pin and via pad stacks.

As in manual placement, the user can interactively route a design before or after using the autorouter. Generally, interactive routing is used to pre-route critical signal nets and supply nets before activating the autorouter. Interactive routing is further used to edit autorouted, but sub optimal, boards or to pre-route traces in difficult areas of high density, e.g., within a grid area or dense connectors with fine pitch. Of course, connections which are left unrouted by the autorouter (shown as overflows) are interactively routed by ripping up traces and re-routing of nets. This work is generally time consuming and needs a great deal of experience.

Autorouting can be done whenever there is a valid complete placement on the board. Before using the autorouter the user should embark on a routing strategy. He should consider his design from an autorouter’s point of view:

• What is the best method of specifying a routing grid and how many layers do we need?

• What technology rules are specified by the manufacturer?

• What are the characteristics of components and connectors on the board?

• What are the general design rules?

The rules have to be carefully defined before starting the autorouter. There are:

• general rules, used in every board of this kind;

• company specific rules, mostly related to quality, soldering and assembly;

• board manufacturer rules;

• application specific rules.

The quality of the design and the costs of manufacturing the board, of later assembly of the components and testing are directly linked to these rules set up. Every bit of manual editing work after routing is time consuming and a high cost factor, besides the risk of introducing new errors. This rule set up is tried to be kept standardized, it will only be slightly changed with different application boards.

The routing algorithms used today are classical maze runner algorithms (e.g., the Lee algorithm), which are steered by cost factors, applied to paths found. These cost factors are directly influenced by the design rules. The Lee algorithm provides a set of equivalent shortest paths for a net. Traces going left to right in a horizontally defined layer are much ‘cheaper’ than traces going up or down, so they are preferred. Each bend in a path has extra costs, vias are expensive too, so they are avoided as far as possible. It is useful to configure the router by redefining these cost factors to improve routing performance, but in many cases the default values are sufficient. Routing performance further

depends on the sorting of the nets in the netlist. Short distance connections are routed first, long distance connections are routed later. The sorting may be influenced by defining nets as critical, and these are routed first. Autorouting is done by several iterations with some rip up mechanism (rip up router) for difficult nets. The router works multi- dimensionally in all layers of the board. Autorouting is stopped when all overflows are routed or if there is no improvement possible after a predefined number of rip up tries. If there are overflows left, they have to be routed manually.

The process contains some heuristics, so it is not possible to an identical routing twice, although the starting conditions are the same. A good placement leads today, with professional systems, to a 100 % resolution, remaining overflows of up to 10 may be acceptable, if there are more the process has to be started again. If there is again no improvement the placement has to be modified or the rules defined have to be checked.

Figure 25.16 shows an example of fig. 25.14 after the autorouting process. Only some few traces have been corrected.

The fig. 25.1 and fig. 25.9 show that in the design process the design schematics and the netlist de- rived from it are the source of all following steps.

Both the simulator, as well as the different layout tools, refer to the schematics. The simulator and the layout tools both use some information from the schematic, for example, the number of components, but not all. Most of the component properties required for simulation as well as for layout are, however, different. For example, geometrical data is normally irrelevant for the simulator, the layout process, however, is essentially based on these data. Therefore the components used in the schematic must contain properties for simulation as well as geometrical data for the layout process.

It is important that changes or corrections are still possible in all phases of the design process. The design must stay consistent. This implies that each design change is administered correctly in a so called back annotation. In fig. 25.9 it is shown that the back annotation process registers all changes which are made during the layout process, and re-report these changes to the schematic. The back annotation process is optional and can be

influenced by the designer. Back annotated data is highlighted or displayed in predefined colours in the schematic in order to flag the change to the designer.

In order to point out the principles of the back annotation process it is described here on the basis of the Mentor Graphics design software.

The goal of back annotation in the Mentor Graph- ics EDA system is:

• to transfer the property information of the cur- rent board design back to the source schematic;

• to pass property values, calculated from the geometric length of the paths, e.g., net delay back to the simulation tool for use in a post-routing simulation.

In the design process a so called design viewpoint is used as a container for all design related data. This design viewpoint is the object in the data model that allows a downstream tool to view the relevant properties of the source schematic. Figure 25.17 illustrates the definition of a viewpoint. The design viewpoint object can be understood as a picture frame through which a downstream tool ‘views’ the source schematic. The viewpoint contains all needed data as a collection of properties for the downstream tools. All tools must view a source schematic through a design viewpoint. Viewpoints can be created and modified with a tool called the Design Viewpoint Editor (DVE); mostly this is done in an automatic way after closing the schematic.

The source schematic itself cannot be changed directly from the downstream tool. The designer is only able to make changes in the schematic by using the back annotation mechanism. If he is working in the simulation tool he may change the value of a resistor by editing the value in the schematic view window of the simulator. This change is recorded in a back annotation object which is part of the design view point.

If the circuit is simulated all model parameters that are necessary for simulation must be defined beforehand. Parameters which are not yet de- fined in the schematic with concrete values have to be assigned in the DVE . Figure 25.17 shows a source schematic as an example, in which the value (X + 5) is not yet defined for X . For the simulator viewpoint the value X = 5 is assigned.

As shown in fig. 25.17, the source schematic is protected in the viewpoint. The source schematic cannot be changed from the simulator tool. But by selecting a property in the simulator schematic view window a change can be made. In this case a delay value was changed from 5 ns to 8 ns, as shown in fig. 25.18. The source schematic stays unchanged, however.

All property changes are stored in the simulator back annotation object (fig. 25.19). At any time the user with a particular viewpoint can update the schematic to the most current version. Viewpoint and back annotation object are closely connected with each other. The modified property values are stored.

The back annotation process covers all tools for PCB design. This should be pointed out as an example. It is assumed that the component values are incomplete in the schematic for a resistor because the circuit is not yet completed. If the layout and the circuit are designed concurrently, the layout tool needs, however, definite names for the geometrical symbols. Therefore the lacking logical symbols are added by the layout tool. It assigns the name R5 to a resistance for example.

After the back annotation process the name R5 appears in the schematic marked in colour.

In this way a certain bottom up design style can be applied which is quite common in PCB de- sign. Connectivity is normally not included in back annotation, therefore a netlist change from a downstream tool is generally not possible.

If during the layout process the properties of components are modified or new properties are added, the back annotation process arranges changes in all relevant viewpoints and program modules and keeps the design consistent. To include these changes in the source schematic a definite decision by the user is needed.

An additional application of back annotation is the method of passing net delay information to the simulation tool for use in post layout simulation of the design. The performance of a circuit can then be verified by consideration of geometrically induced net delays.

The quality requirements of electronic modules and their complexity increase continuously. The development time decreases and the price pressure rises. That is why concurrent engineering is necessary today. This design methodology allows the members of a design team to work in parallel on

the same design and to start downstream processes sooner. Tasks such as simulation and physical layout may start early even when significant modifications still have to be made to the original design source.

Figure 25.20 illustrates how the concept of the de- sign viewpoint makes this possible. The simulator and the layout tool both ‘see’ the source design in their respective design viewpoint. These down- stream tools capture the changes in their respective back annotation objects.

In our example it will be assumed that two de- signers work on the same project. One uses the simulator tool, the other the layout tool. Figure 25.20 shows their individual view of the design source. All changes made to their viewpoints as results of their design work are stored in the respective back annotation objects.

The designer who analyses the circuit behaviour with the simulator has changed the delay value from of 5 ns to 15 ns to evaluate its effect on circuit performance. Additionally, in order to ensure a minimum wire length between the two upper blocks he has pre-assigned the reference designator U1 to this blocks, which tells the layout tool to include these blocks in the same physical package.

The second designer, working with the layout tool, makes some changes from a layout perspective. The bottom two blocks U2 and U3 were defined. Reference designators are assigned to these blocks and a timing value of 8 ns is added to the wire. This value may be calculated by the layout tool from the physical wire length.

Figure 25.21 shows the current viewpoint of the simulator, fig. 25.22 the viewpoint of the layout tool.

The changes are saved in the respective back an- notation objects. They are included in the original schematics if both designers are satisfied with their results and decide to include these design changes into the design object. This represents an incremental concurrent design style.

Output Files

When the design is completed the board is checked by a DRC run. The most important checks are:

• Checking that all traces in the artwork are the same as in the circuit schematics;

• Check for design rules violations.

If the DRC is passed successfully, it is certified that the design can be produced in the intended manufacturing technology.

Now the manufacturing documentation is created. The postprocessor creates files for all layers and several additional manufacturing data.

Examples of manufacturing data are:

• Connection lists;

• Mask description of each layer;

• Soldering masks;

• Aperture table;

• Drill table;

• Placement drawings;

• Fabrication drawings (milling);

• Manufacturing documentation.

The manufacturing data can be directly used to control a photoplotter for mask creation and numeric controlled (NC) machines for drilling and milling.

The manufacturing documentation includes following data:

• Schematics;

• Netlists (EDIF);

• Bill of materials;

• Drill table;

• All drawings.

An extract of a typical bill of materials is shown in table 25.2, sorted according to components (items), and table 25.3 sorted by reference designation. These extracts can be easily generated from the inherent component data base in the design.

Manufacturing data is manufacturer specific and must be adapted to the data formats of the production process. Modern PCB design tools are flexible enough to provide data and formats for all relevant production lines.

The basic steps in creating manufacturing data, sometimes called artwork data are:

• The artwork order must be defined which determines the association between board layers and film layers;

• The aperture table must be defined which establishes the apertures used by the photoplotter;

• The Gerber format files for describing the art- work must be generated. These files are used to control the photoplotter.

The artwork data format must match the format required by the specific photoplotter. This is generally the so called Gerber format, because the manufacturer of a widely used photoplotter is a company called ‘Gerber’ which defined a widely adopted standard. The photoplotter uses apertures to write the masks on the film. These apertures have to be specified in the aperture table, see table 25.4 as an example.

In the second column of table 25.4 the geometrical shape of the aperture is described, e.g., a rectangle or a circle. The size of the aperture in width and height is defined in columns 4 and 5. Column 9 notes the so called Dcode. This value is used for plotting and may be seen again in the plotting file table 25.6. All traces are plotted with a circle aperture which is moved over the film (column 3, trace). All pads are made by a flash projection (flash).

In table 25.4 one row (pos. 16) is marked in grey. In the table the cell at column 8 (Power) and row (pos. 16) is marked ‘true’. This specific aperture is called power aperture. With these apertures pads can be created which are connected to ground or power. The corresponding aperture on the photoplotter used has a user-defined power aperture flash shape which can be used for thermal ties. These shapes may vary. Therefore a number of options exists in defining the final thermal tie shape  on artwork. Figure 25.23 shows an example of a power aperture flash shape with the definition of tie and air gap values as chosen in table 25.4. The term ‘flash’ results from the way these pads are produced: the mask shape is projected on the film with a flash light, giving the complete symbol in one step.

The Gerber artwork format is a description of how artwork data is written to artwork files. This format must match the settings of the photoplotter.

An example of an artwork format report (in the Gerber format) is printed in table 25.5. In this report all parameters needed by the photoplotter are given. The report shows, e.g., that arcs and circles are interpolated by 8 segments. The scaling factor is set to 1.000, the data format version is 5.3, etc.

How a Gerber data file looks is shown in table 25.6, showing a small part of such a file, which is generally in ASCII format.

Drill data and milling data are used by numerically controlled (NC) machines for drilling the through holes and milling the board’s outlines. The format of this data has to match the NC machine’s specifications. Before drill data or milling data can be generated the drill table and the milling table must be defined. These tables are ASCII files generated by the layout software. For example, the drill table associates drill holes in the design with drill bits in the drill magazine. Every drill hole which is required in the design must have a matching drill bit. This step is also referred to as setting up the drill magazine.

Table 25.7 shows an example of a drill table and the related report in Excellon format. This table was created automatically from the layout data and reflects the defined hole sizes in the design rules or used via objects.