Library Design:Library Standards (VITAL)

Library Standards (VITAL)

A consistent and reliable model of digital gates and memory elements is not trivial. In the past several different approaches and modelling languages have been developed for this purpose. Each company which offered a digital simulator developed its own proprietary modelling language and proprietary concepts for capture and definition of delays. ASIC manufacturers are forced to describe their libraries in different dialects, appropriate to the most important EDA sellers. Exchangeability, even a direct comparison of the results, is difficult. So the results of a simulation with a MENTOR GRAPHICS QUICKSIM simulator give significantly different results from one obtained from CADENCE or VIEWLOGIC. Even the logic value systems (12-value logic, 9-value logic, etc.) are not compatible if a detailed analysis was required. Which was right and which company simulate best the real behaviour?

With the definition and standardization of VHDL, a fundamental standard for description of logic circuits was set up. The accompanying packages IEEE 1164 standard_logic define a unified 9-level logic value system [17.6]. One of the most important problems in using VHDL in the beginning of the 1990s was libraries which missed the standardized description of delays. This led to the foundation of VITAL, the VHDL Initiative To- wards ASIC Libraries, in 1992. The goal of this initiative is to accelerate the development of ‘sign off’ quality ASIC libraries in VHDL. The best available procedures and methods for modelling of macro components should be included.

‘Sign off’ quality means that the manufacturer guarantees the functionality of the circuit which has been simulated using these VITAL libraries. VITAL is now a loosely coupled association of ASIC manufacturers, design houses, the EDA industry, and interested users. It is still the goal of this organization to develop specifications and standards concerning this topic.

The first and may be most important result of this work is the IEEE standard 1076.4 with the title: ‘VITAL ASIC Modelling Specification’ [17.12], the last issue 4/99. This standard refers to methods and procedures of the Standard Delay Format (SDF) [17.9], to elements of the std_timing_package of VHDL Technology Group, to the IEEE 1164 standard concerning unified multi value logic systems [17.6], and is last but not least, based on the huge experience gained from existing modelling languages, software tools, and libraries. VITAL is supported by more than 60 companies working in this field. The standardization is not yet finished. The latest supplement, released in 1999, standardizes methods and procedures to describe memories (RAM, ROM).

A direct result of this standardization initiative are VHDL packages which may be bound to the code of the model description and provide declarations and functions for simulation. These packages are:

• IEEE.vital_timing,

• IEEE.vital_primitives.

The intentions of VITAL are going further than only for unification of modelling. VITAL pack- ages should help to perform all other simulations procedures using delay times:

• Definition of timing constraints for synthesis;

• Simulation of real time behaviour on gate level using library elements;

• Pre-setting of timing constraints for place and route;

• Back annotation of timing data after place and route for post simulation;

• Evaluation and assessment of error conditions like set-up/hold violations, glitches, etc., and generation of standardized warnings and error messages.

As a medium for transfer of timing data the generic construct of the VHDL language is used. These values are defined with standardized naming conventions and predefined types. The generics are constants and in this way pre-calculated during compilation of the code. Constants cannot be modified during run time. By this load dependent, temperature dependent, and supply voltage dependent delays are fixed with simulation start. This accelerates simulation significantly.

List 17.1 gives a VITAL compliant description of a NOR gate with 2 inputs (NR2). Library descriptions are typically written not by hand but generated by specialized tools (VITAL_MODELER). These tools add the attributes needed for further synthesis with, e.g., SYNOPSYS automatically (as a commentary, see list 17.1).

Models may be type level 0 or level 1. Level 0 models are relatively simple descriptions. Level 1 models may be quite complicated and use the powerful modelling capabilities of the VITAL definitions (more or less). Figure 17.9 shows a structure of level 1 models.

Input and output signals are declared in the entity (as common in VHDL). Here we find the generics which describe the default behaviour of the gate. The architecture may be of level 0 or level 1.

The first timing block models wire delay. This is the delay of the interconnection structures between cells, not the internal delay. The related generics are set to zero, they will be redefined by back annotation with concrete values after the place and route operation.

The following negative constraint block may contain preset values for logic synthesis and does not exist in all cases.

Now follows a detailed description of the cells behaviour. There are several possibilities. If a VITAL primitive, a cell with the desired function, already exists, it can be called here. Otherwise there must be a behaviour description of the desired functionality in the process section of the VHDL description. The VITAL process contains further a test section for the timing check and a path delay section which describes the signal propagation and by this the behaviour of the output if there are glitches or spikes on the signals. The process construct is a very powerful VHDL statement, able to encapsulate several and complicated functions, tests, and behaviour descriptions.

The process contains in addition some switches which allow to control the deepness of the test mechanisms (Xon), if error checks should be done (TimingChecksOn) or if error messages should be generated at all (MsgOn). These generics may be overwritten and allow to control the model behaviour during simulation.

VITAL timing generics are a combination of pre- fixes, the name of the input pin and the name of the output pin:

has to be interpreted as: delay time between input a and output z. The kind of transition is taken from the type of the variable with the suffix . . . 01. So 01 stands for a transition from the strongly driven output 0 to strongly driven 1, the delay for this is 449 psec, for the opposite transition 1 to 0 a delay of 443 psec (see also list 17.1).

In table 17.11 the VITAL predefined timing generics prefixes are listed.

The VITAL_primitive package contains predefined tables and basic gates (primitives), which can be used to describe complex cells very easily.

• Vital_Primitives.

• VitalTruthTable,

• VitalStateTable.

Table 17.12 shows a list of primitives which are predefined. The most important gates like AND, OR, NAND, NOR, as well as multiplexers and decoders are available.

More complex functions (e.g., AOI gates) may be defined using the VitalTruthTable. Flip flops are not predefined, they must be modelled using the  generalized VitalStateTable function. This func- tion generates Moore automata.

It must be remembered that VITAL does not define a canon of library cells, but provides tools and mechanisms to define consistent, powerful and standardized gate models. The IC manufacturer must describe their library elements with the help of VITAL Packages, the deepness of description may be their own decision.

VITAL gains more and more importance today, not least for standardization of the back annotation mechanism. With modern deep sub-micron processes a significant part of the delay is in the in- terconnection, and so post layout simulation after place and route gains importance. The SDF format for unified description of time data plays here the central role. The relation between the SDF data and the VITAL generics is defined in IEEE 1076, so there is a direct mapping of values.

VITAL, SDF and IEEE 1164 multi-value logic standardize and unify methods and procedures for measuring and definition of timing data and allows timing behaviour to be captured in a quantitative way.

One result of the VITAL initiative is that today company proprietary digital simulators are completely replaced by VHDL simulators with same or better functionality.