Mixed Signal Simulation:Overview

Overview

The term mixed signal simulation signifies a simulation of a circuit where parts of which are described at different levels of abstraction and are simulated simultaneously [12.6]. In this chapter particularly the simultaneous simulation of analog and digital parts of a circuit is discussed.

The necessities and motivations for applying mixed signal simulation to a system are listed below.

• Many important circuit blocks are intertwined analog and digital circuits, e.g., Analog Digital Converters (ADC), Digital Analog Converters (DAC) or Phase Lock Loops (PLL).

• More and more digital circuit blocks are de- scribed at an abstract level, e.g., in VHDL. If other digital and/or analog parts of the system have to be simulated, the result is again mixed signal simulation.

• Sometimes the different parts of a system have a different development maturity. The more elaborate parts are described at a logical level, for instance, whereas other parts are described only at a more abstract level.

• Another reason for using different abstract lev- els is given by complex components (e.g., a CPU) being available only as models at a high level of abstraction whereas other circuit parts have to be simulated at a more detailed level.

• One can reach the optimal simulation speed and accuracy only if the critical parts which deter- mine the accuracy are described at a level of higher abstraction, and therefore can be simulated much faster.

Simulation on different levels of abstraction

The levels of abstraction discussed in this chapter are

• transistor (or circuit) level;

• logic level;

• register transfer level;

• system level (see fig. 12.1) [12.5].

The models in the different levels of abstractions represent different views of the parts of the sys- tem. The quantities used for description differ according to the level of abstraction (e.g., voltages or logic levels, respectively), also to the algorithms applied. Therefore one needs connecting interfaces when simulating at different levels of abstraction. When climbing up the hierarchy the complexity increases, the details are more or less lost, and the simulation effort decreases.

At the transistor (or circuit) level the models of the components are described by algebraic equations often in the form of differential equations. Time and value range are continuous, the quantities used at the analog nodes are voltage and current.

The circuit used as an example for transistor level description in fig. 12.1 represents a two input NAND gate. The performance of circuits of this kind can be checked by analog (or circuit) simulation. For that purpose the simulator has to solve the non-linear, coupled differential equation which describes the circuit. This process is very time consuming. The most popular analog simulator is SPICE.

At the logic level the models of the components are described by Boolean equations, truth tables, rise, fall, delay times, etc. Time and value range are discrete. The quantities used at the digital nodes are named ‘Bit’ and are logic levels, e.g., with the values 0, 1, X, R, F . . . These values can be associated with different driving forces.

The circuit used as an example for logic level in fig.

12.1 represents a D flip flop consisting of NAND gates. It could be possible to simulate one of the NAND gates (e.g., the one leading to the output Q) at transistor level. Simulators for logic circuits mostly use event driven algorithms, which leads to faster simulations compared to analog simulators.Mixed Signal Simulation-0208

At register transfer level (RTL) the models of the components are similar to those used at the logic level but here more complex units are described. An RTL model can be of a structural nature such as transistor or logic level, or can consist of a procedural description, e.g., in VHDL. The connection between the models are formed by buses, therefore groups of bits are combined to ‘bytes’ or ‘words’.

Time and value range on RTL are discrete as in logic level.

The circuit used as an example for RTL in fig. 12.1 represents a CPU consisting of ALU, control unit, register, and I/O unit. If, for instance, parts of the I/O unit are to be simulated in more detail, the necessary latches can be described at logic level.

The simulation on RTL is usually event driven as well which will be faster than at the logic level because the RTL models are less detailed.

At system level the models of the components are similar to those used on RTL but here the units are of even higher complexity. Time and value range are usually discrete. The connection quantities between the models are formed by messages (plain text). The circuit used as an example for system level in fig. 12.1 shows a computer consisting of two CPUs which can both access a common memory. If one of the CPUs is to be described in more detail an RTL model could be used.

The simulation at system level is usually event driven as well, which will be faster than at RTL because the degree of abstraction is higher.

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