Semiconductor Process Technologies:NMOS and CMOS Technology

NMOS and CMOS Technology

Most of the integrated circuits nowadays are produced in MOS technology. The basics of MOS technology will be presented first for the NMOS Silicon Gate technology. In section 19.3.2 the CMOS technology will be described.

NMOS Technology

Figure 19.25 shows the top view and the cross section of an NMOS transistor. The gate, located above the 20 nm thick gate oxide, consists of polysilicon (thickness ca. 400 nm). Source and drain are formed by implantation of arsenic or phosphorus. During this process the channel length L and the channel width W of the polysilicon gate are determined.

threshold voltage for the creation of a channel below a conductor is strongly depending on the 0 doping concentration of the substrate material and on the thickness of the oxide. Figure 19.26 shows  the dependency of the threshold voltage on the  doping concentration of the substrate and on the thickness of the oxide.

PMOS FETs without additional boron doping are principally of the enhancement mode type because there is an accumulation of phosphorus atoms in  the silicon surface at the Si SiO2 interface during the oxidation. On the other hand, NMOS FETs with low substrate doping and even with thick oxides exhibit a conducting channel, which results from the reduction of the boron concentration at the Si SiO2 interface during the oxidation. Doping of the channel regions of MOS FETs is adjusted in general by ion implantation. This is to set the type (enhancement or depletion mode) and the required threshold voltage of these transistors.

Figure 19.27 shows as an example the shift of the threshold voltage VT by implantation of the channel regions [19.4].

Source and drain are bordered through a thick Field Oxide created by local oxidation (LOCOS process). Table 19.2 shows the threshold voltage VT0 of NMOS and PMOS structures as a function of bulk doping and oxide thickness.

The negative threshold voltage of the NMOS structure on weakly doped substrate material shows that there occurs every time an inversion of the surface. This is the reason why below field oxide regions the doping concentration is increased so far by ion implantation of boron (field implantation) until the unwanted inversion is avoided reliably (see fig. 19.25).

The necessary thickness of the field oxide depends on the supply voltage of the circuit. Higher supply voltages require thicker field oxides and/or higher ion implantation doses during the field implantation. The thickness of the field oxide is about Principally transistors in MOS circuits are self- insulating because source, drain, and channel in  normal operation are reverse biased with respect to the substrate (exception: Latch-up in CMOS structures see section 21.1.3). Unlike in bipolar technology, special structures for the insulation of the components are unnecessary. This results in the very high packaging density of active elements in silicon.

The sequence of processing steps of the NMOS silicon gate technology is shown in Figures 19.28 to 19.36. A detailed presentation of the particular steps of photo resist deposition, patterning, resist stripping and cleaning was omitted in these drawings.

Basic materials are weakly doped (p−) silicon wafers. During the first processing cycle the field oxide is grown on the wafers by local oxidation excluding the active areas where the MOS FET will be placed. For local oxidation (see section 19.1.2), a very thin SiO2 layer is grown on the wafers (protecting oxide) and then a Si3N4 layer is deposited above it. By means of a photo resist process the nitride layer is structured in such a way that the Si3N4 is preserved over the active areas (Mask M1, active area).

To increase the field threshold voltage a field implantation (boron) is applied. Figure 19.28 shows the cross section of the transistors active area at this time.

After that the Si3N4 and the protecting oxide are removed and the gate oxide is thermally grown.

For the adjustment of the threshold voltage VT of the enhancement transistors the VT -implantation is applied over the whole surface (see fig. 19.30).

Subsequently phosphorus or arsenic is implanted over the whole wafer. By this process the source and drain regions of the MOS transistors are created (see fig. 19.33). The channel length is determined by the width of the polysilicon gates and thus self-aligned. By this the capacitances resulting from the overlapping of gate source and gate drain are minimized.

In the field oxide regions phosphorus is implanted into the oxide and consequently not electrically activated. Thus the channel width is self-aligned as well and equals the width of the active area.

Now a thermal oxidation is applied, during which the open monosilicon and polysilicon areas are covered by a thin protective oxide (about 0.1 μm), whose function is explained later on. At this state of processing the wafers are covered by relatively thick oxide layers with steep edges of oxide and polysilicon. These are very disadvantageous for the deposition and structuring of the metal inter- connect lines. It may even happen that the thick- ness of the metal layers is significantly reduced at the oxide edges.

ture of the reflow process may be further reduced (about 900 ◦C). The thin protecting oxide, mentioned above, has to be created before the deposition of the silicate glasses, because during this high temperature process unwanted doping atoms could diffuse out of the glass into the silicon beneath it.

The mask following now (M4, contact windows) opens the contact windows to the poly and mono- silicon (see fig. 19.35). At the same time the edges of the oxidation steps are rounded by an appropriate technology. In addition, after the etching procedure the oxidation steps are rounded again by a further reflow process.

After the structuring of the contact windows, aluminum with added silicon (ca. 1 %) and copper (ca. 2 ... 4 %) is deposited on the wafer by sput- tering and structured by a further mask (M5, metal mask) (see fig. 19.36). After tempering of the wafer for the reduction of the contact resistance between aluminum and silicon a protecting oxide is deposited over the metal lines.

By means of the final mask process (M6, Pad windows) the areas (pads) for the bonding wires, which connect the chip with the case are opened.

The minimum number of mask processes steps is six and thus is well suited for the production of complex VLSI circuits. This number increases if other types of structures are needed as, e.g., direct contacts between poly- and mono-silicon or for further metallization layers.

A modification of the NMOS process, the LDD technology (Lightly Doped Drain, see fig. 19.37) [19.7], is used especially for modern components with very short channel lengths (< 1 μm). The goal is to realize a flat doping profile of the PN junction at the drain side of the channel instead of an abrupt one. This helps to avoid the shift of the threshold voltage due to hot carrier degradation in transistors with very short channel lengths.

Using the LDD technology the wafers are processed including polysilicon patterning. Then phosphorus is implanted with a much lower con- centration than normally used for source and drain (see fig. 19.37a). Then with a Low Pressure Chemical Vapor Deposition process (LPCVD) an oxide with a thickness of about 0.25 μm is deposited. The oxide covers the oxide step on the wafer very smoothly (see fig. 19.37b). Subsequently the oxide is stripped in a anisotropic dry etching process. That means the vertical etch rate is much higher than the lateral etch rate. The oxide thickness is bigger at the sides of the polysilicon stripes than on horizontal areas. Oxide stripping is done in such a manner that the thinner oxide is removed whereas the thicker oxide partly remains in areas at the sides of the poly silicon stripes. These oxide residues called ‘Spacer’ act as distinct broad- ening of the polysilicon stripe during subsequent high dose source drain arsenic implantation. That means that between the rim of the channel and the highly doped arsenic zones there are low phosphorus doped stripes. In this way the unwanted high doping concentration just at the side of the channel can be avoided.

The following process steps are the same as with the normal NMOS technology.

In complex circuits the number of components per chip is limited by the maximum permissible power, which can be dissipated by the case. By the use of CMOS circuits essentially less power dissipation is possible as with NMOS circuits. The technology needed for CMOS is presented in the following section.

CMOS Technology

CMOS technology allows realizing NMOS FET as well as PMOS FET on the same chip. Figure 19.38 shows the cross section of a CMOS inverter. The process used, is derived from the NMOS technology. For the P-channel FET there is created a weakly n-doped area (‘n-well’) into which the PMOS structures are inserted.

Besides the n-well process there are still two further variants of the CMOS process. The ‘p-well process’ starts from an n-doped substrate wafer and uses a ‘p-well’. This technology is not directly compatible with the NMOS technology and shows some electrical disadvantages. It is used rarely. Much more frequently used is a process with two wells (n-well and p-well), called ‘Twin Tub Process’ which is discussed shortly at the end of this paragraph.

In the n-well CMOS process the n-well is con- nected by a (n+)-contact with the source of the PMOS FET. The field oxide regions are created by local oxidation. A field implantation is only applied to the (p−)-surfaces. Frequently additional guard rings are used to prevent Latch Up. The function of this measure is explained in detail in section 21.1.3. Because of that these guard rings are not mentioned while the CMOS technology is described. They may be created by the process steps discussed subsequently and require no additional process steps.

Sequence of Process Steps of the N-Well CMOS Technology

Substrate material is a (p−)-doped silicon wafer.

The wafer is oxidized and then the windows

For the local oxidation of the field oxide zones the oxide is removed from the wafer surface. Then there is grown a thin protection oxide and subse- quently Si3N4 is deposited on the whole wafer.

Finally, there is a pyrolytic deposition of the protecting oxide and the opening of the pad windows by a mask (M9, pad mask).

As can be seen, the CMOS process requires nine masks at minimum plus a maximum of two masks for the adjustment of the threshold voltage of the transistors. For each of additional metal layers two additional mask processes are required.

Twin Tub Process

Alternatively to the n-well process described above there is increasingly used a CMOS process using two types of wells (Twin Tub Process). Using local oxidation the structure shown in fig. 19.54 re- quires only one photo mask process to implement the two ion implantation steps for the two wells

 

After implantation of boron and photoresist strip- ping follows a first p-well drive in and simultaneously an oxide is grown selectively over the p- well areas (see fig. 19.56). Thereafter the nitride is removed and (without a further photo process) phosphorus is implanted for the n-wells (see fig. 19.57). In an additional drive in diffusion process both wells are diffused into the silicon until the required junction depth is achieved (see fig. 19.58). The oxide is removed then from the surface of the wafer.

The further process steps correspond with the n- well process after implementation of the n-well. The surface impurity concentrations of the well regions may be adjusted for the required thresh- old voltages of the NMOS and PMOS transistors. The highly doped substrate improves the stability against latch-up of the CMOS structures (see section21.1.2).