Digital Simulation:Structure of a Digital Simulator

Structure of a Digital Simulator

Every powerful development environment (work- bench) for ASICs or FPGAs uses simulators. They are indispensable for circuit design at the complex level which integrated circuits of modern technologies. In this case the simulator already has the appropriate interfaces to the other development tools of the workbench. If the simulator needs data for timing simulation of the circuit, they are extracted from the layout and processed for the use of the simulator. If a simulator of a different development environment is used, the specific data must be adapted using pre or post processors.

Simulator for Logic Circuits for Verification of the Design A simulator for logic circuits is an interactive program which uses a model of the circuit de- signed.

The circuit description, assumed to be in HDL (hardware description language), is the source for building the circuit specific simulation model (fig. 11.4). Logic elements are in the model li- brary which is specific to the technology used

to implement the ASIC. This task is performed by a program with similarities to a compiler for programming languages. It is necessary to build a specific model for simulation of a circuit. A universal simulator, which has to be tailored to simulate the behavior of a specific digital circuit, would use too much memory and its simulation speed would be too slow.

The kernel of the simulator calculates the reaction of the circuit according to the stimuli created by the designer. Depending on the data available for the logic model, different results will be obtained. Determined by control instructions, a simple functional simulation with unit time delay for each logic gate or flip flop can be executed. If timing data are available, timing simulation is able to produce results close to the real circuit.

The huge number of gates in an ASIC requires a decision by the designer about which part of his system he wants to simulate and at which level of accuracy in the development cycle. The simulation time depends greatly on the accuracy of the models and the complexity of the circuit. The cost for generating test stimuli and simulation time must be appropriate to the goal of verifying the intended function of the circuit. This trade off is difficult to evaluate in different design phases.

To achieve testability an ASIC must be designed in modules from the very beginning. The pre- tested modules are combined into a system whose function also has to be verified. The input pattern for testing, the stimuli, are defined as programs in a specific language or may be designed and modified using a graphic interface. There are tools for automatic generation stimuli.

The simulator calculates the reaction of the circuit to the test stimuli. The designer controls the type of simulation to be performed. He decides which part of stimuli is used and, in particular, which signals are displayed and documented as results. The user may specify any external or internal signal of the circuit to be displayed on the screen. For debugging it is advisable to select only relevant signals.

A difficult task is to evaluate the results of simulation and to decide if there are no faults within the design. The designer knows the function to be implemented, he also defines the test stimuli, and therefore he can check the simulated circuit reaction. If there are data available for direct comparison, from a description of the function in a different language like VHDL, both results can be compared automatically on the workbench.

Definition of Logic Levels (Logic Values)

Both terms logic level and logic values are considered equivalent.

The high number of gates in digital circuits demands in comparison with analog simulation a reduction of the accuracy for the logic values used in a simulator. The number of different logic values processed in a simulator must be adjusted to the necessities of different stages of the development cycle. The simulation time of circuits can be shortened considerably by reducing the number of logic values simulated. However, the designer has to assess that the simulation result still shows correct reactions of the circuit to be verified.

The simplest simulator for digital circuits uses only two different values, namely 0 and 1. 0 represents the range of voltage recognized by a specific tech-

nology as a logic 0. If a TTL-compatible circuit is used this range is from 0 V to 0.8 V.

A simulator which uses a two-value logic system simplifies every output of a logic gate and every state of a flip flop to a 1 or a 0. It is obvious that for a circuit with flip flops this is an insufficient description. After ‘power on’ the output of a flip flop may be 0 or 1 which can not be described appropriately.

A three-value logic system has the additional value X (0 or 1). A signal having a value X means that its logic value is unknown. It may be 0 or it may be 1. This value is shown graphically in simulators as a patterned area (fig. 11.5). Depending on the logic function an X may propagate to the output of a gate. In the literature different terms are used for this logic value. U (unknown logic value) is also used as a different term instead of X. The value U alternatively designates an uninitialized value in literature. For the user the logic system of a simulator is explained in detail with the expressions used in the relevant manuals.

X describes the behavior of hardware more de- tailed than only 0 and 1. But there are small differences. If a flip flop with two outputs q and /q is inspected, both outputs are X after power on. In a real circuit /q is the inverse q. The value X does not contain this information.

In simulation it is useful to assign a unit time delay for every gate or flip flop. The execution time is greatly reduced compared to simulators using individual time specifications. At an early stage of development simple faults such as missing variables or a wrong logic definition are recognized by using three-value logic and unit time delay simulation.

If more complex structures are analyzed, the value Z (high impedance) allows the simulation of the behavior of bus structures. The value Z may be either a logic 0 or a logic 1, or neither a 0 nor a 1. It will be processed in the simulator to evaluate the reaction of the circuit. It represents a bus which in reality is not driven by any circuit. It may represent any voltage in the range of a given system between 0 and Vcc. Naturally simulation time increases if four-level logic system is used in a simulator.

An example of the use of a six-value logic sys- tem is the Design Centre (PSPICE), an industry standard for simulation of analog circuits. The six logic values are given in table 11.1.

For example, by using R the rising edge of a signal is modelled.

A simulator must take into account how a logic level will be evaluated in regard to the respective driving circuit. If a signal is connected to Vcc with a pull up resistor and will be connected to ground by an active transistor, then it will change its value depending on the greater strength of the transistor. Another attribute is logic strength which is defined for a more accurate simulation of logic circuits.

In Verilog, eight different values are defined to describe logic strength (table 11.2).

It is remarkable that the logic strengths 4, 2, and 1 are assigned to capacitors. The capacity of interconnections in a chip can thus be taken into account in simulating a circuit.

The result of digital values can thus be calculated with higher accuracy. This system is suitable for modeling CMOS circuits with transmission gates and tri-state circuits for busses.

If the logic AND gate is simulated the output value is resoved by a table (table 11.4).

But if these logic values are used who will pro- vide the necessary models and their parameters for simulating a real circuit. The model parameters depend on the logic function and the technology used for implementation. With the growing standardization of model libraries this problem will be solved gradually. One important step in this direction is the IEEE Std_Logic_1164 Pack- age, in which models for logic standard functions and their various kinds of parameters are defined. These definitions allow simulation in a nine-value  logic system. Generally the designer depends on the model library attached to the system he uses for circuit development.

Performance of a logic simulation

The first simulators calculated signal values for every single node of a circuit in a time scale. This leads to simulation times which are not accept- able. Nowadays event driven simulators are used. Only if there is a change at the input of a logic component like an AND gate or a flip flop will a new logic value for the corresponding output be calculated by the simulator. Only those components are treated which are driven by the changing signal. In parallel, a timing wheel takes track of the elapsing time to represent the time scale chosen by the designer for his simulation process. All events are documented in an event list or event queue with the time related to the event.

Fault Simulation for Verification of Fault Coverage of Test Stimuli The effectiveness of test stimuli can be evaluated with fault simulation.

The theory of fault simulation is described in detail in chapter 15.

For the fault simulation a circuit specific simulator will be compiled using the circuit description and the model library of the development environment. The designer decides which fault models of the

fault library or of interest should be used for fault simulation.

A simple logic fault model for verifying the effectiveness of test pattern is the ‘stuck fault’ model. There is the s.a.0 fault (stuck at zero) fault which assumes the logic value of a specific node per- manently to be 0, which means it is connected to ground. If an s.a.1 fault (stuck at one) is inserted the node will have a permanent 1, that is, it is connected to Vcc.

Generally, single stuck faults are assumed for fault simulation. One fault is inserted and the fault simulator simulates the behavior of the complete circuit under this circumstances. The test stimuli are applied to the external inputs of the circuit now called primary inputs. The reaction of the circuit will be observed at the external outputs of the circuit, now called primary outputs (fig. 11.7).

Naturally, before integrating a module into a complete circuit it can be treated likewise in order to evaluate the effectiveness of the test stimuli.

For reference the fault simulator will simulate the reaction of a fault-free circuit at every node. For each single fault inserted the simulator will simulate the respective faulty circuit again and monitor the circuit reaction. In order to save simulation time parts of the circuit which are not affected by the fault will not be simulated. If the simulated value at a primary output deviates from the respective value of the fault free circuit, simulation  is stopped and the fault will be marked on the fault list as ‘detected’.

To save time several faulty circuits are simulated parallely in a system.

More details about fault simulation are described in section 11.7 using example circuits.

Performance and Use of Logic Simulation

Two simple logic circuits, an AND with inverter and an R-S latch are used to demonstrate performance and use of logic simulation. The simple circuits are chosen to put the performance of a simulator into foreground and not the circuit by its complex function.