Digital Simulation:Design Example,16-bit Counter with Carry

Design Example:16-bit Counter with Carry

Sequential logic is a challenge for testing because the state of the storage elements and the input combination determine the next state of the circuit. The sequence of test stimuli greatly affects its effectiveness. A 16-bit counter is used because its function is well known.

If one wants to set a sequential circuit to a specific state sometimes many test vectors have to be applied in a definite sequence. A 16-bit counter is a good demonstration of the benefit of a scan path. Moreover, it shows clearly that dividing the 16-bit counter into modules of 4 bits simplifies the design of the test pattern.

Module 4-bit Counter

The 16-bit counter will be designed by using 4 identical modules of 4-bit counters. The correct function of the 4-bit counter has to be verified once and henceforth it may be used multiply without additional effort.

Functions of the 4-bit counter

The 4-bit counter module (fig. 11.37) was synthe- sized by Autologic (Mentor). With signal rb = 0 (r bar, active low) the counter is reset to 0000b. Clock input is cp (clock pulse). If the input en = 1 (enable) the counter will count up. For en = 0 the actual state does not change with the clock. Output

co (carry out) is set to 1 after the change of q3 ... q0 from 1110b to 1111b. The counter has a scan path. To scan data in, sde = 1 (scan data enable) is used. Data of the input sdi (scan data input) are clocked in serially with clock cp into the flop-flops of the module.

Design of the first test stimuli for the 4-bit counter

The following considerations influence the design of test stimuli. With rb = 0 the 4 flip flops are reset to 0000b. For every state of the counter it is necessary to find out if it does not change while en = 0. The carry bit must be activated. To achieve the necessary states the designer draws up the necessary test vectors (list 11.10). Comments explain the vectors described. There effectiveness of test stimuli is checked with fault simulation

As explained previously, in fig. 11.34 untestable faults are outputs with no connections to elements. Obviously their behavior can not be observed at primary outputs. Possible faults will be explained later in this chapter. To find out undetected faults the schematic is examined Most of the undetected faults are connected to the scan path which was not activated until now. The histogram (fig. 11.39) shows that after test vector 92 no additional faults have been detected. Activating test vector 92 the counter reaches 1111b. The test vectors after test cycle 92 can be deleted without affecting the number of detected faults.

Explanation of test vectors

Every fault simulator produces a timing diagram of the fault free circuit with the given test stimuli. This timing diagram is used to discuss the test vectors and the reaction of the circuit.

Applying the first test vector with rb = 1 and the rest of the input signals are 0, the output signals with undefined (depicted with an arrow between 0 and 1) will go to 0. With rb = 0 the circuit is reset and all outputs remain at 0. If rb goes to 1 again, it becomes inactive. The next vector is the first of a loop which is executed 18 times, en = 0, and the counter will not count with the next positive clock edge. Thus there is no change created by the next test vector in which cp goes to 1. Neither does the next test vector change any value when cp returns to 0 again. But the following test vector sets en to 1 and therefore q0 goes to 1 with the next clock pulse. Clock cp goes low again and nothing changes. This was the first pass of the loop which will be executed 18 times. There are 6 test vectors for each pass in which the counter is incremented.

As mentioned before, the schematic shows that faults which belong to the scan path are not detected. Which raises the question of why the scan path has not yet been used in test. Because each state of the counter and its transition to the following state must be tested, naturally this test is performed by incrementing the counter. Therefore it is not necessary to reach a distinct state of the counter using the scan path. But the situation is different if at state 1111b the function of the reset will be tested. In this case, to reach 1111b from 0000b, 15 clock pulses are necessary which must be compared with 4 clock pulses to scan in 1111b directly. Obviously the scan path reduces the number of test vectors greatly. This will be explained in what follows.

In complex circuits scan path is state of the art.

Some details to possible faults

It is interesting that 4 % of the faults are called ‘possible faults’.

Possible faults will be explained according to the definition in the fault simulator Quickfault:

Possible faults are faults which are related to the hardware test of the finished circuit.

They are related to the reset path of this counter, that is to the paths which deal with signal rb (fig. 11.41).

What is the special quality of a possible fault? If the power supply is switched on the output value of a flip flop is undefined, it is either 0 or 1. After reset the output q of every flip flop is set to 0. If accidentally the output value of the flip flop is already 0 and at the same time there is a fault in the reset path, a test system would recognize the expected correct value 0. In this case a test system would not detect the fault with this test vector. That is why this sort of fault is called a possible fault.

If the test program is improved the number of possible faults will drop to 0 and the number of detected faults will increase.

Improvement of test stimuli

With the help of the scan path the test stimuli are enhanced. If all flip flops with the help of the scan path are set to 1, then after reset all q outputs of the flip flops will go to 0. If there is a fault in the reset path this fault will be detected and the possible fault will be removed from the fault list.

In addition the scan path is activated for the first time. All flip flops are set using sdi, which is the serial input of the scan path. With this action faults of the scan path will be detected likewise.

Using scan path the counter is set to 14, 1110b (/* data shift */). This state could be reached similarly by counting but this comparable procedure needs more clock pulses.

Subsequently the counter counts to 15 (/* next state */) and is reset afterwards. Test vectors of the enhanced test stimuli are in list 11.12.

4-bit counter with enhanced test stimuli: fault coverage of 100 %

With the additional test vectors all s.a.0 faults and s.a.1 faults are detected. The number of detected faults increased to 186 because all possible faults could be detected. Consequently their number dropped to 0 (list 11.13). Note that the number of untestable faults is still 8, because the outputs have not been connected to primary outputs.

An additional look at the timing diagram shows the behavior of the fault-free circuit. Taking the originally designed test pattern, the final state of the counter is 2, that is 0010b (fig. 11.43). To clock in test data sde must be 1. At the same time the signal en must be 1 during the process of loading flip flops as well. To load a 1 the signal sdi must be set to 1. With the next clock pulse a 1 is shifted in the first flip flop of the scan path. The result is the state 5 which is 0101b because the 1 of q1 was shifted with this clock pulse into q2. After reaching state the 1110b the scan in process is finished with sde = 0. The counter reaches 1111b with the next clock pulse and the signal carry changes to 1 as expected. In this state the function of reset is tested with rb = 0. With this test vector all s.a.1 and s.a.0 faults in the reset path are detected.

Design Example 16-bit Counter

The advantages of a modular and structured design using pre tested modules are demonstrated in the following. The 16-bit counter is designed with cascaded modules of the 4-bit counter.

Specification of the 16-bit counter

The new module 16-bit counter (fig. 11.44) uses the same inputs as the module 4-bit counter: rb, en, cp, sde, sdi.

The counter is reset with input signal rb = 0 (reset bar). The clock is connected to the input signal cp. Only if en = 1 is the counter counting up. To use the scan path the input signal sde must be set to 1. The 4 modules of 4-bit counters are concatenated, forming a serial path. The input signal sdi provides the serial data for the scan path. Output q3 of 3 modules are connected to input sdi of the subsequent module. Counter outputs are q15 ... q0. Serial data out of the scan path is q15 of the counter.

Advantages to use scan path for fault simulation of the 16-bit counter

The counter could also be tested just by incrementing the counter using 65536 clock pulses. Additionally control signals like input en would have to be changed equally, which adds up to a huge number of test vectors. This number of test vectors could be reduced greatly by utilizing scan path.

In order to test the function of the 16-bit counter all carry out signals co must function and be processed likewise correctly by the subsequent module. As an example the output signal co of the third counter module, which is called icnt20, is considered. The output signal co is called ncra2 and is connected to logic which controls the input en of the fourth module called icnt30. If this carry would be activated by incrementing the counter, 32768 clocks would be needed.

If the scan path is used only 16 clock pulses are applied to set the state for testing ncra2.

In the following all flip flops are loaded by using a macro in order to keep the loading procedure standardized.

Macro for loading the counter

The scan path is used many times in testing. It is useful to write a macro for loading the counter.

The macro is called SCANin (list 11.14). The state of the counter is the parameter id15,... ,id00 and it is loaded serially through input sdi. To enable loading, sde must be 1. Here is an example for loading the counter with 0000000011111111: the macro call is SCANin(0.0.0.0.0.0.0.0.1.1.1.1.1.1.1.1).

The most significant bit that corresponds to output pin ra15 is the first bit to be loaded. It is the first 0 in this pattern. Clock pulses are included in the macro.

Testing least significant 4-bit module icnt00

At the beginning of the test the least significant 4-bit module icnt00 is activated. The first part of the test is the same as the one for the original 4- bit counter. That shows that using modules is an additional advantage in test pattern design. Scan path is not yet used.

Testing carries between 4-bit modules

The functions of three carry bits ncra2 . . . ncra0 have to be tested. The procedure is explained for icnt10. The initial state fort his test is 00ffh. Scan in is switched off by sde = 0. With en = 0 and cp = 1 the counter must keep its state unchanged for this test vector. The next test vector is cp = 0 and en = 1. With the following cp = 1 the counter counts to 0100h. The same procedure applies for the other modules.

Testing individual modules icnt30, ..., icnt10

Module icnt00 was tested already with the test vectors of the original 4-bit counter.

The other tree modules are tested in a similar way. For this purpose a structure for testing is set up in (table 11.8).

Details of the test vectors are explained on the basis of the module icnt20. By means of the scan

path the pattern 00ffh is loaded. With en = 0 and cp = 1 the counter must keep its state. The next test vector with cp = 0 and en = 1 prepares counting. With cp = 1 the counter will count to 0100h. After that test the counter is loaded by the scan path with 01ffh. Serial loading is switched of with sde = 0. Again, the next test vector with cp = 0 and en = 1 prepares counting. With cp = 1 the counter will count to 0200h. At the end of this part of the test cp is reset to 0.

The similar procedure is performed for icnt10 and icnt30.

Testing the remaining undetected faults

With the test vectors there are three faults left undetected in the circuit (list 11.15).

The three faults are at the inputs of the AND gates (an04d1, an03d2) controlling the input en of module icnt20 and icnt30 (fig. 11.45). In order to detect these faults the outputs ncra0 and ncra1 must be forced to 0. The signals refer to the inputs A2 of the AND gate an03d2 and the inputs A3 und A2 of the AND gate an04d1 (fig. 11.45). This can be accomplished by the three test vectors in list 11.16. Because of the explanations of the macro SCANin the commands need not be discussed in detail.

The result of the expanded test shows fault coverage of 96 % (list 11.17). Untestable faults refer to the outputs which are not connected to primary outputs. As explained previously the possible faults are the s.a.0 faults of the flip flops. If additional test vectors similar to the test of the original 4-bit counter would be added, a fault coverage of 100 % is achieved.

Final Remarks to the Fault Simulation of the 16-bit Counter

All faults are detected. Untestable faults and possible faults had not been removed. The structured approach listed in table 11.8 shows the structure of the test program for fault simulation. After reset of the counter the first counter module icnt00 is examined. Before testing the other counter modules, the carry bit between two counter modules is activated. Now the counting of the modules icnt10, icnt20 and icnt30 is examined. Finally, the three remaining faults are checked by forcing specific carry bits to 0. This procedure can be modified for testing similar structures.

In fig. 11.46 a histogram shows the distribution of numbers of detected faults related to individual test patterns.

Necessity of Various Design Tools in the Design Process The way in which a designer designs his circuit greatly depends on the workbench and the tools he uses. Logic simulation and fault simulation are essential as powerful tools in the development process of a circuit.

There are several approaches to describing the function of a circuit. In many areas source code for describing a circuit usually is written in VHDL. It is still necessary to analyze the synthesized circuit at the schematic level during the verification process. A designer who has to write test vectors for his circuit depends in many cases on the hardware which was being synthesized.

The display of a histogram shows clearly the effectiveness of the test vector and helps to optimize the test procedure. Faults printed into a schematic help to identify the problems associated with them. Therefore graphical representation of complex results is an important feature which eases the use of design tools.