Application Specific Integrated Circuits (ASICs):Economical Aspects.

Economical Aspects

In this section ASIC design styles will be dis- cussed with respect to economical aspects. The costs of ASIC manufacturing, which generally alter rapidly, are not often published by the semiconductor manufacturer. Thus the following values can only be considered as approximate.

ASIC as Product

At first some terms will be introduced which are related to the evaluation of costs and profits of ASICs.

‘Fixed costs’ (FC) are those costs of a product, that are independent of the number of parts sold. With ASICs there are, for instance, the costs of masks or of the CAD installation. The fixed costs have to be taken into account in proportion to every IC sold.

‘Variable costs’ (VC) are those costs of a product, which are proportional to the number of parts sold. With ICs there are, for instance, the costs of a die or a case. Generally the lifetime of a product on the market is restricted and superseded by better successor products. This lifetime is called ‘product lifetime’ (PLT). Within PLT a certain number of parts of a product will be sold. This is called ‘sales volume’ (SV).

The costs per IC are found by

Fixed Costs

Training comprises acquaintance of the technology related design kit, which contains the design rules and the libraries and, in addition, getting to know EDA tools, computers, and system organization are taken into account. The more specific the tools, the higher the training costs.

The costs for computer and software include the costs for buying a workstation and the license costs for EDA tools. The proportion of these costs is dependent on the project time, which differs with each of the design styles.

The design costs comprise the costs for design staff and costs for generating the layout of the ASIC. The starting point for table 16.3 is a medium sized ASIC with 20,000 gate equivalents. In order to estimate the number of days required for the design it is necessary to have an idea of the productivity, i.e., the design speed (gates/day) which is dependent on the design style. In addition, the  experience of the designer, the design method, and the EDA tools play a role.

Part of the design time is needed to design the testability of the IC and to generate the so called test vectors.

In addition to the design time of the original circuit the time for evaluating the IC samples and for a possible redesign has to be taken into account. This effort regarded to be proportional to the effort of the original design.

The non-recurring costs for production of an ASIC are called Non-Recurring Engineering Costs (NRE). These comprise the generation of custom specific masks the number of which is dependent on the design style. The information about masks cost is related to a technology with a feature size of 0.35 μm. In addition, the cost of the production of some ASIC samples and the costs of test related preparation and programming were added to the NRE. Not taken into account were costs for the so called industrialization which qualification and investigation of production methods under different conditions.

Other fixed costs comprise costs for documentation, marketing and advertising. Here the figures vary so much that it does not make sense to insert concrete values.

If the evaluation of the ASIC samples show that the performance of the IC does not fulfil the expectations, the design has to be improved. Especially with full custom design the probability of a redesign is high, because untested cells are used. With semi custom ICs the test results are normally in accordance with the simulation results found during the design. Every redesign causes costs for design and NRE. More important, however, is the resulting time loss and the lower product lifetime of number of parts.

The total fixed costs are the sum of training costs, computer and software costs, design costs, mask costs, cost for test preparation, and other costs.

Variable Costs

Table 16.4 gives an overview of the variable costs of an ASIC related to different design styles where some data were taken from [16.10].

In order to determine the cost of a die the required area of the die is calculated first. For this purpose the number of gates is divided by the gate density and multiplied by the density factor. The gate density and the density factor of the layout are dependent on technology and design style.

Figure 16.14 shows a wafer with medium sized dies (left) and large dies (right). The dots represent defects caused by errors during production. The dies near the periphery are incomplete and cannot be used. The number of complete dies is given by complete dies

The defect density is a quality feature of the technology. A singlee defect on a die will generally make the die unusable. In order to avoid too high a failure rate with a 0.5 μm technology a defect density of less than 1/cm2 is necessary.

The yield is dependent on defect density (Dd) and die area (DA) [16.4]:

For an established technology a yield of more than 80 % is expected. The number of intact dies is calculated by multiplication of the number of whole dies with the yield.

The costs per processed wafer refer to an 0.5 μm technology. The costs per die are finally deter- mined from the costs per wafer divided by the number of intact dies.

The package costs are approximately proportional to the number of pins but also depend on form  and material of course. The numbers given refer to rather cheap SMD plastic cases.

The last row in table 16.4 shows the test costs per IC. Every single IC is tested by means of test vectors.

The total variable costs of an IC are equal to the costs per die, case costs and package costs.

Design Style Comparison

With the data provided in section 16.3 the IC costs can now be determined according to equation  16.1). Figure 16.15 shows the IC costs as function of the sales volume during the lifetime of an IC for the different design styles, in which the fixed costs  were taken from table 16.3 and the variable costs from table 16.4.

With increasing sales volume the fixed costs are less significant and the IC costs decrease. At a sales volume of approximately 1,000 the break even volume (BEV) between the FPGA and the gate array design style is to be found. Referring to the above data, the BEV between gate array and standard cells or macro cells lies at 10,000 parts.

Only above 100,000 parts does the full custom solution become optimal.

There are a few ways of lowering the IC costs. The fixed costs are mainly determined by the design productivity. For this trained designers, modern design methodology, and good EDA tools are necessary. The costs of masks and of sample production can be lowered if the concept of a so called multi-project wafer (MPW) is applied. Here several different designs can be processed on one wafer. Also for production of a low number of parts or in the starting phase of a product the MPW can be an attractive approach.

The price of an IC is determined by the IC costs plus the required profit per part. The achievable price mainly depends on competition, which in turn depends on when the innovative product is put to market. The following consideration highlights the design speed as the decisive factor in the success of an IC.

Figure 16.16 shows the monthly sales of a product first under the assumption of an early introduction to the market, second with later introduction [16.2]. If the product is introduced later the product lifetime will be shortened from tPLT1 to tPLT2. In addition this product will have a lower market share. Both factors lead to a loss of turnover and lower the sales volume.

The design styles presented differ in design and production time tE: for the exemplary ASIC the FPGA solution required a design time of 48 days and no time for production whereas the full custom design solution required 520 days design time and 50 days production time. Of course, distributing the workload to several designers can shorten the time required for the development of an IC.

It becomes clear that a combination of different design styles is of great advantage. In order to achieve a fast product introduction a FPGA or gate array solution could be chosen, whereas for mass production a solution with lower variable costs is appropriate.

The design methodology has to be chosen in such a way that a change in design style does not lead to too high a development effort.