Circuit Verification:Verification with Programmable Devices.

Verification with Programmable Devices

A quite different method of design verification is to implement a prototype using programmable de- vices. Such a PLD (Programmable Logic Device) consists of a certain number of configurable logic blocks which can be configured to behave like an elementary gate or to perform more complex logical functions. Furthermore, the logic blocks contain sequential elements (flip flops). The logic blocks are connected by a configurable interconnection network such that according to the specific configuration the logical behavior of any circuit can be modeled.

There are different types of programmable devices. In the case of an FPGA (Field Programmable Gate Array) the configuration is stored in a RAM and can easily be changed an arbitrary number of times. Therfore the FPGA may be used for an inexpensive circuit verification even in an early phase of the chip’s design. For example, the behavior of a combinatorial logic block with four primary inputs and two primary outputs can be configured using a RAM (Random Access Memory) with 24 = 16 data words of width 2 bits. Into this 2 × 16 = 32 bits one stores a complete function table representing the intended behavior of the logic block. During operation the input data x1, x2, x3, x4 are applied to the address lines of the memory and its data output drives the primary outputs y1, y2 of the logic block.

For other types of memory such as PROM (Programmable Read Only Memory) or EPROM (Erasable PROM) one obtains non-volatile programmable devices.

Although there are essential differences between PLDs and ASICs, programmable devices are used for design verification because there are fast and easy methods within ASIC design systems to convert an ASIC design into a PLD configuration. Using this approach a PLD can be used as a prototype implementation of a design.

Essentially, the verification method is to apply sample inputs to the programmable device and to compare its outputs with the expected values. This is very similar to the methodology of verification by simulation. Therefore, as described in section 9.1, there is the problem of selecting the most relevant input patterns. Although a PLD is much faster than a circuit simulation it is impossible to apply all possible sequences of input patterns.

One has to distinguish between two applications of programmable devices. First, they can be used as a so called hardware accelerator for simulation. In this case one needs a special simulation software to use the FPGA as a co-processor performing time consuming simulation tasks. In this way the designer can use the front end of a logic simulator, but results are computed much faster, therefore more extensive simulations become feasible. De- pending upon the selected signals to be monitored and on the desired accuracy, the complete circuit, or only some sub-circuits, are performed on the FPGA. In this way the only advantage of the programmable device over the simulation software is the reduction of computation time.

A second more interesting approach is to use an FPGA prototype within the desired hardware environment of the ASIC. Then it is also possible to test the interaction of the circuit with other components. As a simple example we consider the control of several 7-segment LED displays using a multiplexing method. Normally a simulation will produce a sequence of output patterns, and the designer has to decide whether the patterns are correct. For example, he has to decide whether the data is applied to the correct display and whether the correct segments are selected. Furthermore, he has to decide whether the signals are consistent to the LED specification and whether the timing of multiplexing is well chosen, so that the display is bright and does not flicker. To check automatically all these effects by simulation a very fine modeling of 7-segment displays would be necessary.

ment of a circuit has to be modeled for simulation, which in most cases cannot be done in practice. However, the designer can obtain the same in- formation by directly testing the prototype within the target hardware, or at least within a simplified environment on a demonstration board.

Thus the main advantage of a prototype is to check the interaction of a circuit with other components already available. This way one can also detect design errors that are the results misunderstandings of the specification and that cannot be found by simulation.

A problem of verification with PLDs is the different timing of ASICs and PLDs. This is because in a PLD every sub-circuit is implemented by reading results from a look up table. Thus the switching time of a logic block does not depend on the complexity of the modeled sub-circuit.

Since the interconnection between logic blocks consists of pre-defined wire segments connected or separated by transistors, the distribution of net capacities for a PLD is quite different from that of an ASIC, resulting in different signal delays. Only a small modification of the circuit can result in a quite different allocation of sub-circuits to logic blocks, producing large differences in the length of wires. For an ASIC the same modification may only locally affect few signals.

Thus a PLD implementation of a prototype is not suitable for checking the exact timing of a circuit design. In particular, one cannot determine the maximal possible clock rate of an ASIC by investigating the behavior of a PLD prototype.