Semiconductor Process Technologies:Basics of the Silicon Planar Technology (SPT).

Approximately up to the year 1970 integrated circuits were realized mainly in bipolar technology. Though the basics of MOS technology already were known, the reproducibility of the threshold voltages of MOS-Field Effect Transistors (MOS- FET) was insufficient. The problem could be solved, however, with the breakthrough of the ion- implantation technology. Since that time MOS is the dominating technology for the production of integrated circuits.

For analog circuits the most important technology still is the bipolar technology, because the transconductance of Bipolar Junction Transistors (BJT) carrying a comparable amount of current is much higher than that of MOS FET [19.8]. Additionally for high output currents the chip area needed for BJTs is less than that for MOS FETs.

A combination of both technologies is achieved on the one hand by the BiCMOS technology (Bipolar- CMOS) [19.21] combining CMOS circuits with BJTs (NPN and PNP types) and on the other hand by the BCDMOS technology [19.10] which combines on a single chip bipolar transistors with CMOS circuits and additionally (for high voltages) with DMOS transistors. But both technologies are very costly and are implemented only if all their advantages are required.

First of all, the following paragraphs present the silicon planar technology and its processing steps. Thereafter the processing steps for bipolar and MOS circuits are presented. These presentations are completed by the description of components, which can be integrated on a chip.

Basics of the Silicon Planar Technology (SPT)

Introduction

The realization of modern monolithic integrated circuits is achieved mainly by the SPT. Integrated circuits for very high frequencies are realized most often by the GaAs technology because of the high electron mobility of this material.

Using SPT the active regions of the IC are generated close to the surface of the mono-crystalline silicon wafer. To achieve that, doping materials (B, P, As, Sb) are introduced by solid-state diffusion or by ion-implantation into the surface of the wafer thereby changing the concentration and the type of the majority charge carriers (either electrons or holes). Silicon oxide can be easily grown by thermal oxidation of silicon on the surface of the wafer. This material (SiO2) is nearly impermeable for the doping materials normally used in silicon. The atoms of the doping material can pass only through windows in the silicon oxide layer created by a photolithographic process using a photo mask. The process steps and their sequences for the production of bipolar and CMOS circuits are presented in detail in the following paragraphs.

Oxidation

For the oxidation of the silicon surface the wafers are exposed in a tube of quartz glass within an oxidation furnace at temperatures from 900 to 1200 degrees centigrade. The oxidizing atmosphere consists either of oxygen (dry oxidation) or of water vapor (wet oxidation).

In the latter case the water vapor is created by controlled burning of hydrogen and oxygen inside the oxidation tube.

The rate of oxidation rises with the temperature (see fig. 19.1) and is dependent on the atmosphere in the oxidation tube. Dry oxidation results in low oxidation rates with high quality of the oxide. With wet oxidation the oxidation rate rises rapidly but the quality of the oxide and of the silicon-silicon dioxide interface is lower than of dry oxidation.

To increase the gas pressure within the oxidation tube results in raising the oxidation rate as well. Examples for oxide growth using High Pressure Oxidation are shown in fig. 19.1 as well.

During the oxidation all silicon areas are oxidized, either they are pure or are coated by a SiO2 layer. Selective oxidation [19.22] of distinct regions is achieved by coating the areas not to be oxidized with silicon nitride which is impermeable for oxygen and thus prevents the underlying silicon areas  from being oxidized.

Figure 19.2 shows schematically the processing steps for a local oxidation (LOCOS) without (left hand side) and with (right hand side) pre-etching of the crystal silicon.

First of all a thin protection oxide layer is grown. Above that silicon nitride (Si3N4) is deposited which has been structured by a photo lithography process (see fig. 19.2b).

During the following oxidation process the Si3N4 layer prevents the oxidation of the silicon surface (see fig. 19.2b). The oxide grows a little bit under the Si3N4 layer (see fig. 19.2c) thereby creating the so-called bird’s beak structures. Later on the nitride and the protection oxide are etched off and the gate oxide is grown (see fig. 19.2d).

By the use of silicon pre-etching the height of oxide steps may be decreased. But a totally planar surface cannot be achieved by this method.

For the structures to be transferred onto the wafers a photo lithography process (mask process) is used. The photo mask consists of a quartz plate, which is coated by a thin chromium layer. The desired structures are transferred to this layer by electron beam writing. Figure 19.3 shows the steps of the mask process for the transfer of structures into an oxide layer.

First of all a thin layer of photoresist (PR) is put onto the oxidized wafer (see fig. 19.3a). This is done by putting some drops of the PR onto the wafer. These are then equally spread over the complete wafer by fast rotation (spinning). In the next step the PR is exposed to ultraviolet light

By development of the PR during the next process

step the exposed parts of the PR are removed from the wafer (see fig. 19.3c). On the wafer remain only the areas of the PR, which were hidden by the mask (unexposed areas) (positive PR). Alter- natively with the negative PR procedure the unex- posed areas are removed from the wafer.

By means of this the PR keeps a positive or a negative image of the photo mask structures.

Thereafter the PR is hardened by heating. With the PR as a mask the desired patterns are then etched into the oxide using a liquid containing hydrofluoric acid. Figure 19.3d shows a cross section of the wafer after the removal (‘stripping’) of the PR.

The contact printing lithography depicted in fig. 19.3b has the disadvantage that the mask touches the PR coated wafer during exposure causing rapid contamination of the mask by sticking particles of  the PR. This is the reason why in modern processes the mask is projected optically onto the wafer [19.15].

During the projection exposure the whole mask is put as an image, scaled 1 : 1, onto the wafer. The disadvantages of this method are the low depth of focus and the low optical resolution because of the large image area, especially when large wafer diameters are used.

For very small structures (< 1 μm) the projection exposure has been replaced by the use of wafer steppers. Applying this technique, only a small part of the wafer (about 14 mm × 14 mm) is exposed with a much better resolution. Thereafter the exposing field is stepped under laser control to the next section and focused. Then this next section is exposed and so on. By the application of wafer steppers even uneven surfaces may be compensated for and the resolution is much better than with the 1 : 1 projection exposure.

The masks are adjusted automatically with reference to the existing structures with tolerances < 0,2 μm. The photo masks are patterned by electron beam writing. Targets are chromium plated quartz plates, coated with resist layer which changes its structure under the exposure to the electron beam. The electron beam is electromagnetically deflected under the control of the mask data processed by the electron beam writer. After the electron beam writing procedure the parts of the resist not touched by the electron beam are removed. The resist is hardened by heat and with the resist as a mask the underlying chromium layer is etched. The resolution of this process is < 80 nm.

Doping

Bulk doping of the silicon wafers is accomplished already during the growth of the silicon mono- crystals. Important doping substances for silicon are boron (B) as an acceptor for p-conduction and phosphorus (P), arsenic (As), and antimony (Sb) as donors for n-conduction. Figure 19.4 shows the resistivity as a function of the doping concentration in n-type and p-type silicon [19.12].

At high temperatures (900 ... 1 200 ◦C) doping atoms may move from the wafer surface into the silicon supported by voids in the silicon lattice. This movement is called solid state diffusion. Thereby the doping concentration is highest at the surface and decreases with the distance from it. Figure 19.5 shows as an example the concentration of boron in an initially n-type wafer doped with arsenic.In cases of predominant boron concentration silicon is p-conducting. In cases of predominant arsenic concentration silicon is n-conducting. The pn-junction is formed just at the location where the boron and arsenic concentrations have the same value. The corresponding value of the penetration depth is the ‘junction depth’ x j of the pn-junction

The introduction and distribution of the doping substances in a solid state diffusion process is achieved mostly in two steps. First of all with the pre-deposition diffusion (‘Pre-dep’) the doping atoms are introduced into the wafer. Many wafers are exposed at the same time to an atmosphere containing the doping atoms. Adding oxygen to this atmosphere creates an oxide saturated with the doping material. This oxide forms the source for the actual solid-state diffusion. The Pre-dep creates a constant surface concentration of the doping material, which corresponds to the solid solubility of the doping atoms in silicon at the process temperature. Therefore the surface concentration of the diffused layers is high (> 1020 cm−3).

Figure 19.6 shows the normalized doping concentration profile as a function of the penetration depth [19.13].

After the Pre-dep the oxide, saturated with doping material, is removed by etching. Then in the following ‘drive-in’ diffusion process at high temperature and without additional doping material the doping atoms penetrate deeper into the wafer. The amount of doping material in the semiconductor is nearly constant during the drive-in process but the junction depth increases and the surface concen- tration decreases.

One of the disadvantages of the solid-state diffusion is the relatively high tolerance (about ±10 %)

of the sheet resistance of the diffused layers. Significantly smaller tolerances may be achieved by the use of ion-implantation.

Figure 19.7 shows schematically the cross section of a diffusion furnace. The wafers are placed in the quartz tube at right angles to the stream of the gas. The doping substances flow as hydrogen compounds into the tube and decompose at the high temperature in the furnace. The doping atoms are built into the silicon dioxide surface layer cor-responding to their solubility

Ion Implantation

For direct inserting doping atoms into the silicon the solid state diffusion is more and more replaced by the process of ion implantation (see fig. 19.8). In an Ion-Implanter the ions of the doping material carrying mostly a single charge are accelerated in a vacuum by voltages of typically 10 ... 150 kV.

In the mass spectrometer unit behind the acceleration device the ions (depending on their mass and charge) are forced on arcs of a circle with different diameters (without decreasing their speed) by a magnetic field perpendicular to the beam. Owing to this the electron beam fans out and through a hole in a screen only the wanted type of ions can pass. The ions with their high kinetic energy are targeted to the surface of the silicon, penetrate into it, and are slowed down hitting the atoms of the netic energy, i.e., the acceleration voltage of the ions but also on the types of ions and on the deceleration medium. Figure 19.9 shows a doping

Table 19.1 shows some values for the mean penetration depth and the standard deviation of the penetration depth of ions of important doping materials, as functions of the acceleration voltage The lattice structure of the silicon is damaged by the impact of ions. To repair these destructions, the wafers are exposed to temperatures of 600 ... 800 ◦C for about 10 to 30 minutes. During this anneal process the lattice destructions are restored and the doping atoms are positioned regularly in the structure.

In Bipolar Technology as well as with rising frequencies in CMOS technology there is the need for weakly doped layers located on strongly doped substrates. These layers are grown on the wafers by epitaxial processes.

During the epitaxial process a mono-crystalline layer is grown on a mono-crystalline substrate continuing the orientation of the substrate crystals in the epitaxial layer. To achieve this the substrate wafers are exposed to a gas atmosphere containing a compound of silicon with hydrogen with chlorine.

Figure 19.10 shows the scheme of an epitaxy reactor. The silicon compound is decomposed at high temperatures (1,100 ... 1,150 ◦C) at the surface of the wafer. Silicon is deposited and grows on

the substrate. To dope the epi layer a carrier gas containing the desired doping atoms is added to the atmosphere, which is decomposed at the wafer surface setting free the doping atoms. During this process the doping atoms are directly built into the lattice structure of the epitaxial layer. The doping concentration is adjusted by the composition of the gas.

By this means even weakly doped layers may be grown on highly doped substrates.

Metallization

The conductors on IC’s must fulfill different re- quirements listed below:

• High conductivity;

• Low contact resistance metal silicon;

• Good adhesion on silicon dioxide;

• Good covering of the oxid steps;

• Must be suited for multi layer metallization;

• Low electro migration.

The wiring of integrated components on a chip is mostly accomplished by aluminum conductors. For each of the requirements mentioned above, there are particular materials suited better than pure aluminum. But aluminum is a good compromise for the requirements altogether.

Aluminum has a low resistivity (2.7 μΩ · cm ⇒ 50 mΩ /D with a layer thickness of 0.5 μm). Additionally the contact resistance to the (n+) and (p+) silicon is sufficiently low (Rc ≈ 10−7 Ω · cm2) [19.16].

By modern magnetron sputtering processes for layer deposition the step coverage is much better than with the vapor deposition process used ear- lier. Unwanted layers may be removed by back- sputtering techniques before new layers are de- posited. This causes very low contact resistances between the metal layers in multi-layer metallization.

Very small contact windows and/or shallow pnjunctions may cause problems resulting from micro alloying [19.1], [19.17]: during annealing, a process step to decrease the contact resistances,  at temperatures of about 420 ◦C, crystal silicon diffuses into the conductor aluminum. The problem may be reduced by adding 0.8 ... 1 % silicon to the aluminum because then the aluminum is

always saturated while it is deposited and therefore only very little aluminum diffuses out of the wafer surface. The silicon is added to the targets for the sputtering process and is transferred together with the aluminum onto the wafers.

Problems with the metal lines caused by electro- migration can emerge from shrinking structures. High current densities and high temperatures in the metal lines may cause a transport of line ma- terial in the direction of the electron movement. Inhomogenities at this transport may cause interruptions of the lines and thus failing of the device (Attrition of integrated circuits) [19.2]. Figure 19.11 shows an aluminum line without the covering oxide after the application of a high current density (106 A/cm2) and of a raised temperature.

On the one hand hillocks were created, on the other hand an interruption of the line occurred.

Electromigration may be reduced substantially by alloying 1 ... 4 % copper into the aluminum. By means of this the mean lifetime of the metal lines may be increased up to a factor of 1,000.

To prevent electromigration the maximum permissible current density is limited to about 1,000 A/mm2 corresponding with 1 mA/μm2.

The actual value depends on the type of the manufacturing process, the composition of the material, and the operating temperature of the lines.

The limit above must be checked during the design process, which causes a lot of computing time for the design rule check of the layout.

Recently copper lines are in use for ICs as well be- cause of the lower specific resistance and the better electromigration properties as compared to aluminum. The application of copper allows smaller cross sections of the lines in combination with shrinking structures.

Polysilicon and Polycides

In modern CMOS technologies polycrystalline silicon layers (Polysilicon) are used for the gates of MOS transistors (Silicon Gate Technology). Polysilicon is deposited by decomposition of Silan (SiH4) at the surface of the hot wafer (600 ... 650 ◦C) in a CVD process (Chemical Vapor Deposition) [19.18]. The sheet resistance is then adjusted by ion implantation. Gates and short interconnection lines should have low layer resistances. With a layer thickness of 0.5 μm a sheet resistances of 20 Ω /D may be achieved. For long lines polysilicon is not suited because of its in comparison with aluminum high sheet resistance.

The sheet resistance may be decreased by the creation of silicides on the polysilicon composed of titanium, tantalum, wolfram or molybdenum. For this purpose the particular metal is deposited on the polysilicon and subsequently sintered into its surface. In this way the desired heavy metal silicide is created with specific resistances ranging from 20 Ω · cm with titanium silicide (TiSi2) to 100 Ω · cm with MoSi2 [19.19]. For TiSi2 a sheet resistance of 0.8 Ω /D is calculated for a layer thickness of 0.25 μm. The sandwich structure Metal Silicide on Polysilicon is called Polycide as well. For resistors with high resistances there is used low-doped polysilicon too