Semiconductor Process Technologies:Bipolar Technology

Bipolar Technology

Process Description

Bipolar technology uses mainly the processing steps required for the production of insulated NPN Bipolar Junction Transistors (BJT) on a chip. Figure 19.12 shows in perspective the cross section

of an integrated NPN BJT in Standard Bipolar Technology.

The components of an IC are insulated by reverse biased PN-junctions surrounding the particular device. To achieve this a (n−) layer is deposited on a (p−) substrate wafer by epitaxy (‘Epilayer’). Additionally (p+) zones (‘Isolation’ zones) are diffused from the surface through the epilayer down to the substrate. By this means the n-zone is bordered in all directions by a pn-junction (‘n-well’).

Using planar technology the transistor zones are contacted at the silicon surface. Therefore the n- well, which forms the collector zone, is contacted by a (n+) diffusion zone.

The doping concentration and the thickness of the epilayer are determined by the required breakdown voltages of the devices within the n-wells. To achieve a low resistive path for the collector cur- rent, a highly doped (n+) layer is diffused into the substrate, the so-called buried layer, before the deposition of the epi layer. Its effect on the component properties is discussed later on in the context of the properties of the integrated devices.

Standard Buried Collector Process (SBC-Process)

The process is designed to manufacture integrated transistors with VCEo > 20 V.

The sequence of production steps is as shown in figs. 19.13 to 19.19:

• Substrate wafer P type (boron), 5 ... 10 Ω · cm

• Thermal oxidation: 1,100 ◦C, 2 h, oxide thickness tox = 1 μm

a) Mask M1: Buried Layer (see fig. 19.13): (n+)-diffusion (arsenic or antimony), 1,200 ◦C, 10 h, xj = 5 μm, Rs = 10 ... 20 Ω /D, then strip- ping off the oxide. The atoms of arsenic or antimony diffusing slowly are used to prevent the unwanted redistribution of the buried layer into the weakly doped epi layer during the following high temperature processes.

c) Mask M2: Isolation (see fig. 19.15): Diffusion: p+ (boron), 1,100 ◦C, 3 h, xj = 10 μm, Rs = 20 Ω /D; afterwards oxide stripping to de- crease the height of oxide steps on the surface;

Annealing the metal lines at about 400 ... 450 ◦C to minimize contact resistances. Deposition of the protecting oxide over the metal lines.

a) Mask M7: Pad Window

Oxide removal from the areas for the placement of the bonding wires for the connection of the metal lines on the chip to the case contacts.

Testing and Housing

The finished dies (chips) are tested on the wafer and the faulty ones are marked. Afterwards the wafers are put onto a thin film, fixed by adhesion. Then the dies on the wafer are separated by sawing up the wafers in the so called scribe lanes using a diamond saw. Meanwhile the chips remain in order attached to the film and may be picked up for housing or to be mounted on a metal strip.

The Standard Bipolar Process consists of a mini- mum number of seven masking steps. Frequently it is expanded by two additional mask processes to realize highly doped (low resistive) connections between collector contact and buried layer (mask M2a between M2 and M3) and high resistive implanted resistors (mask M3a between M3 and M4).

Integrated Components

As presented in the preceding paragraph the pro- cesses for the production of integrated NPN BJTs are the basic technology of the Bipolar Process. If required, it may be extended by some additional process steps. In the following paragraphs the structures and properties of integratable compo- nents using the Bipolar Process are explained.

NPN Bipolar Junction Transistor (NPN BJT)

The NPN BJT is created in the weakly doped epitaxial layer as a double diffused transistor. Figure 19.20 shows the perspective view of the structure of a double diffused NPN BJT in Standard Technology. The base width is less than 0.5 μm, for transistors with transit frequencies fT > 10 GHz even less than 0.1 μm.

The BJT function, i.e., the movement of electrons from the emitter through the base to the collector, takes place in the region below the emitter zone (‘Inner transistor’). The emitter area is the effectively the area of the transistor.

The Buried Layer decreases the series resistance between the inner collector and the collector con- tact and reduces the current gain of the parasitic Substrate PNP BJT (SPNP, see 19.2.2.3). This parasitic transistor is activated during the saturation of the NPN BJT.

The maximum permissible reverse voltage is given by the breakdown voltage of the plane collector junction and is determined therefore by the doping concentration and thickness of the Epi layer, which covers the Buried Layer. The process as described before yields breakdown voltages of the plane col- lector PN junction of about 90 V. This corresponds to VCEo values > 20 V when the DC current gain is B = 70 ... 150. But the measured breakdown voltage of the collector junction is only about 60 V owing to the junction rim curvature determined by penetration depth of the PN junction. The breakdown voltage of the emitter junction (owing to the higher doping concentration) is less than that of the collector junction and is about 7 V.

Power transistors are produced with multiple emitters in parallel to increase the lengths of the out- lines of the emitters. Additionally they are surrounded by a closed ring of (n+)-doped material, which extends down to the buried layer in order to decrease both the collector series ohmic resistance and the current gain of the parasitic SPNP. Both effects reduce the saturation voltage, which results in a higher maximum permissible collector current.

In the base zone created by diffusion or ion implantation the impurity concentration decreases from the emitter to the collector edge. The concentration dependent rearrangement of the majority carriers in the base causes a ‘Drift Field’ which shortens the transit time of the electrons through the base and thus increases the transit frequency fT.

Lateral PNP-Transistors

Figure 19.21 shows in perspective view the structure of a lateral PNP BJT (LPNP). The (p+) emitter zone is surrounded closely by a (p+) doped collector. The base is formed by the epi layer, which is connected via the buried layer with the (n+) base contact. In fig. 19.21 the inner LPNP transistor is marked by dotted lines. The distance between both (p+) zones, i.e., the base width WB, depends on the breakdown voltage required for the LPNP because the collector depletion layer extends into the base.

This is the reason why WB-LPNP » WB-NPN. Nevertheless the current gain BLPNP ≈ BNPN. A large disadvantage of the LPNP is, that having the same overall chip area its maximum collector current is only 1/10 of the value for NPN BJT. Furthermore, the transit frequency of the LPNP is essentially lower than that of the NPN BJT because of the large base width and because of the absence of a

19.2.2.3 Substrate PNP Bipolar Junction Transistor (SPNP BJT)

Figure 19.22 shows the substrate PNP transistor (SPNP) in perspective. The inner transistor is marked by dotted lines. The emitter is the diffused (p+) zone. The base is formed by the n-doped epi layer and is contacted by the (n+) zone. The collector is formed by the p-substrate and by the p+ isolation zones. The collector is consequently connected to the substrate and not available as an insulated contact. In general this transistor is used only for special applications, e.g., emitter follower stages.

The maximum permissible current of the SPNP is comparable with that of an NPN transistor as are the current gains. But because the base zone is essentially wider and has no drift field (unlike the NPN transistor) the transit frequency is also essentially lower than that of an NPN transistor. It holds

Structures comparable with those of the SPNP are inevitably created between the base and isolation zones of the NPN BJT and between collector and isolation zone of the LPNP BJT. These Parasitic Substrate PNP transistors get into the active mode only if the collector junction of the NPN or LPNP transistors is forward biased, i.e., if these transistors are saturated. A part of the base current flows then through the parasitic SPNP transistor directly to the substrate, which is the most negative point of the supply voltage.

Integrated Diodes

Most PN diodes are created by the use of NPN

transistors having a short circuit between base and collector. Their forward voltage drop equals the forward voltage VBE of the transistor. This con- figuration is advantageous in that the transistor is operated in the active region and therefore the par- asitic SPNP cannot be activated. The disadvantage of this configuration is the low break voltage of the diode which equals the breakdown voltage of the emitter junction which is about 6 ... 7 V. For diodes with higher break voltages LPNP transistors may be used with short-circuited base and collector as well and a supplementary deep (n+)- diffusion around the collector to minimize the ef- fect of the parasitic SPNP transistor.

Z-diodes may be realized with NPN transistors, having short-circuited base and collector and re- verse biased base-emitter junction. The Z-voltage is 6 ... 7 V, depends on the technology, and is of very good reproducibility.

Schottky diodes are created at the contact between aluminum and the low doped n−-type epi layer.

The depletion layer of this junction allows break- down voltages > 20 V.

To create non blocking ohmic contacts between aluminum and n-type silicon the contact area must be (n+)-doped. By means of this the thickness of the depletion layer becomes so thin that it may be tunneled in both directions by electrons and the current is independent of its direction.

Integrated Resistors

Integrated resistors in bipolar technology are most often realized as p-zones in an n-well (see fig. 19.23). The PN junction between resistor body and n-well is reverse biased by connecting the well contact to a voltage level which is equal to or higher than the most positive voltage occur- ring in the resistor body. The sheet resistance of the resistor body (RsR = 1 ... 5 kΩ /D) is most often higher than the base layer sheet resistance (RsB = 100 ... 300 Ω /D). During the layout of the resistors, first of all the resistor body is drawn as a path which is characterized by the width and length of the center line, frequently as meander to save area on the chip. Then the resistor heads and the  n+ well contact are added as preconfigured structures from a library including contact windows and metal contacts. Finally the edge of the separation around the structure is inserted.

The collector junction is used with a capacitance of 150 pF/mm2. The emitter junction is used with a capacitance of 150 pF/mm2. But its series resistance is higher and the breakdown voltage is lower than in a).

In this case the PN junction between the emitter- and isolation-diffusion and in parallel with it the PN-junction between the isolation and buried layer is used. The capacitance increases up to 1,500 pF/mm2. The breakdown voltage decreases to about 5 V.

Even a thin isolator layer (additional process step) between emitter diffusion and metal layer consisting of SiO2 or Si3N4 may be used. This results in specific capacitances of 350 pF/mm2 (SiO2) and  700 pF/mm (Si3N4) when the isolator thickness  Generally only very limited values of capacitance may be realized in integrated form.