EDA Tutorial:Implementation of the Design using the High Level Language VHDL

Implementation of the Design by Schematic Entry

All schematics are designed and input into EDA using the schematics input tool Design Architect (Mentor Graphics) one after the other. Figure 26.4 shows one sheet with the central dice counter FSM circuit.

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The logic may be designed with classical logic design methods by hand or derived from the state diagrams using supporting programs, e.g., LogIC. This is done by further dividing the blocks into sub blocks until a design by hand is feasible and well known and proven circuits can be used. Verification of these circuits, sub-blocks and blocks is nowadays done by functional digital simulation.

The result of this classical structured method is 230 gates, see table 26.1 for a statistics of the used gates.

The result is now transformed in a netlist (e.g., EDIF) and available for further processing.

Implementation of the Design using the High Level Language VHDL

As an alternate design approach to schematics input the design is described block by block in VHDL. In contrast to the schematic style the de- scription is much more abstract, the FSM may be defined in a general formulation, and a detailed dissolution in single gates is not needed. List 26.1 shows an extract from the resulting code, describing the dice counter FSM.

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Each block is described by its own code and verified by digital simulation. The blocks are arranged with the help of a tool for VHDL block design style (RENOIR, Mentor Graphics) into a complete structural description fig. 26.5.

The programming tool RENOIR now generates the structural VHDL code shown in list 26.2, instantiating the components w_counter_decoder, nco_8bit, counter_6_bit. The example is not complete and describes only a part of the entire design to keep transparency. Of course, the code may be written by hand in the same way. The tool RENOIR allows one to arrange and administer the building VHDL blocks in a hierarchical way, which eases supervision in complex designs. Also in Mentor Design Architect, a tool which is used mainly for graphical symbolic schematic entry, blocks written in VHDL may be combined with schematics blocks build up from gates and flip flops. But Design Architect is oriented primary towards symbols and does not have all the special features for VHDL checking like RENOIR. Similar tools are available from other EDA providers too.

RENOIR allows one to input and display state diagrams graphically. The main dice counter FSM may be input in this way directly (fig. 26.6).

Finite state machines written in VHDL may dis- played too, the description forms text or diagram are directly related to each other and show different aspects of the same contents.

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