Semiconductor Process Technologies:Further Enhancements of Technology

Further Enhancements of Technology

The technologies discussed above for bipolar and CMOS circuits offer good compromises with respect to the requirements of the circuits. Many different ASICS may be realized by these technologies. It should be mentioned that the separate development of the two technologies (Bipolar and CMOS) prevailing in the past, is no longer continued and that they merge into combined technologies. Advancements of the MOS technology are adapted for bipolar circuits as well (e.g., local oxidation). On the other, hand typical techniques used in the bipolar technology (e.g. buried layer zones and epitaxial layers) are increasingly introduced into the CMOS technology (e.g., Twin Tub process).

For further enhancements of the technology there are three main targets:

• Shrinking of the structures for higher complexity of the ICs;

• Higher transit frequencies;

• Extension of the operating range of the supply voltages.

Examples of advanced technologies are presented in the following paragraphs. It should be kept in mind that the improvement of one parameter may cause a degradation of other parameters. Most often the improvement of some properties causes a higher number of process steps.

Bipolar Process

for High Frequencies

To achieve smaller structures in bipolar technology, on the one hand progresses in the photo lithography are applied. On the other hand, the diffused isolation zones are replaced by oxide zones which extend down to the substrate and are created by local oxidation. This requires a considerable reduction of the epilayer thickness and of the junction depth of base and emitter thus reducing the breakdown voltage of the devices.Semiconductor Process Technologies-0135

tion of the diffused (p+)-isolation zones a considerable shrinking of the structures and reductions of the junction capacitances are achieved. Moreover the reduction of the junction depth and the use of arsenic emitters lead to steeper doping profiles in the base zones of the transistors. This causes a stronger drift field and consequently a higher transit frequency. All together transit frequencies of greater than 20 GHz may be achieved. As men- tioned before the smaller junction depths cause a reduction of the breakdown voltage and thus demands smaller operating voltages of the IC’s.

BiCMOS

Additional to the improvements in the shrinking of structures in MOS technology there are efforts to combine digital and analog circuits on a single chip. For analog circuits, e.g., bipolar transistors are advantageous because of their much higher transconductance as compared to MOS FETs car- rying the same current. Therefore by the BiCMOS technology CMOS structures and additional bipolar transistors may be realized on the same chip. Figure 19.60 shows cross sections of transistors manufactured by this technology [19.23]. Not only NMOS and PMOS FET but also bipolar junction transistors may be realized. The example shows  an NPN BJT but also Lateral PNP BJTs may be realized by this technique.

The CMOS n-well process has been extended in  this case by three mask processes (Buried Layer, Deep (n+)-Diffusion, P-Base for the NPN BJT) and by the corresponding implantation and diffusion processes as well as by a (p−)-epitaxial layer.

Semiconductor Process Technologies-0136

Besides the BiCMOS process discussed here, process sequences were developed allowing the realization of Bipolar, CMOS, and DMOS transistors simultaneously. This BCDMOS technology is very costly and is used for Application Specific Circuits (Asics), e.g., in automotive applications. Details of this technology may be found, e.g., in [19.10].

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