Library Design:Analogue Libraries.

Analogue Libraries

Analogue circuits are, when compared to digital circuits, much more difficult to standardize. One reason for that is that many circuit elements must be varied in their parameters. A resistor may take every value between some ohms and some megaohms. Low ohmic resistances are very different in lay out as well as in electrical behaviour from high ohmic resistances. Further requests on these elements like ‘matching’ are unknown in the digital domain.

Although there are fundamental differences, the advantage of a set of proofed and characterised basic cells is so big that libraries are used also in the analogue domain. There may be a smaller set of different types. Compared to standard cells these analogue blocks are not same size and must be placed in a block style methodology. Table 17.13 gives a summary of a typical analogue library for mixed analogue/digital ASIC design.

All cells are available as shapes (abstracts) or in the form of a complete lay out description in GDS II format. Additional there are model descriptions in SPICE format and sometimes in VHDL-AMS. In many cases the schematics are available. The cells are accompanied by a data sheet with the most important technical characteristics. All cells are specific to a certain process and it needs a lot of effort to port them to a new process. Cells as a/d converter and as d/a converter are usually typical IP (see chapter 7) and may be acquired by licensing. They are not included in basic analogue libraries any longer.

Resistors, capacitor and standard transistors are not part of the libraries. They are not drafted by hand but generated by lay out generators. Figure 17.10 shows the screen of the IC Station tool (MENTOR GRAPHICS) with a transistor generator in action designing a NAND gate from schematics. This is called schematics driven lay out. The transistor dimensions ‘L’ and ‘W’ are specified as properties in the schematics. The transistors lay outs are generated from this in all mask levels. Electrical connections are displayed as overflows (this is a symbolic display of connectivity in the form of rubber bands). The transistors may be moved and placed everywhere on the silicon, the overflows being routed by hand or automatically.

In the same way resistors and capacitors are generated. The final size and form depends on the parameters taken from the schematics. This idea of using generators can be applied to more complex circuits as operational amplifiers, and comparators too, but this belongs more to the IP domain. Tools like IC Station allow one to edit and manipulate lay out data of analogue cells in a convenient way.

A further, more automatic, generation of analogue lay outs is unusual and makes no sense. There are too many different geometrical limitations, requirements for matching of elements, and many other conditions to follow, which prohibits further automatic lay out generation. Analogue lay outs, mostly full custom and limited to some few cells, will still require the specific VLSI design skills of the engineer.

Library Design-0043

Macro Libraries

Macros are combinations of basic cells in a defined manner to a new function. There are:

• Hard Macros; and

• Soft Macros.

A hard macro is a complete new cell which is build up hierarchically from basic cells and which is completely placed and routed, and as a direct result is ready for placement. Examples of these kinds of hard macros are ALU, adder, or entire processor cores (see before). Hard macros are handled like normal cells, placed by the cell abstract and integrated into the cell interconnection. Today hard macros are called IP and are the subject of commercial trading (see chapter 7).

The characteristics of Soft macros is that they consists of available basic cells, but the interconnection is defined in a netlist. Placement and routing is not pre defined and still open for further manipulation. Examples are counters, registers, and several other building blocks, which are used several times in digital circuits. Classical soft macros are the building blocks of the MSI TTL series 74xx, which are well known to the designer from older discrete designs and which in arrangement and grouping are always a good selection. Soft macro libraries based on the 74xx-family can be found by many FPGA vendors, because many designs were a direct translation of existing discrete designs in the beginning. The importance of these libraries has decreased with the use of high level design languages as VHDL. Larger soft macros are today traded as soft IP, they should no longer be called libraries.

The 74xxx family libraries are more or less re- placed by the LPM standard, a Library of Parameterised Modules. LPM is approved by EIA as an intermediate standard and is seen as a supplement of the EDIF standard (Electronic Design Interchange Format). The LPM standard describes functions built up of basic cells which are com- bined in a netlist to more complex functions. Examples are adders, multiplexers, etc. Because of standardization, LPM functions may be transferred from one vendor to the other. They can be placed in schematics as graphical symbols and do not re- quire further details, only parameters as bus width, type, etc. Mapping to the specific technology may be carried out by the technology provider in an optimised way. LPM functions are supported in the form of generators by every EDA provider to- day: Cadence, Mentor, Exemplar, Summit Design, Synopsys, Veribest etc.

The primary goal of the LPM standard is a technology independent design with high efficiency in the design tools. The designer may use the LPM modules without knowing all the details of the technology. Mapping and fitting to the target technology is carried out by the synthesis tools. LPM today describes 25 functions, amongst them arithmetic functions, adder and multiplier, multiplexer, decoder but also sequential circuits as counters and register files. Because the modules may be parameterised by their architecture style, bit number, and input combinations, the number of functions which may be generated is very large.

LPM functions are also available as VHDL libraries, generated in a structural VHDL style automatically. The VHDL language supports this idea by the generate statement directly. All EDA providers support this kind of design style today.

Design with LPM modules still belongs to the bottom up design style using schematic block diagrams and loses importance in the future with a more system oriented design flow.

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