Design for Testability:Boundary Scan

Boundary Scan

For the Boundary Scan method [15.31] additional cells are inserted between a circuit and the pads on a chip, thus separating the circuit from its environment. In this way a chip can still be tested when it is already assembled within a larger system. Furthermore, the Boundary Scan can be used to check the wiring on a Board or to test a complete system. Indeed, testing complete systems was a particularly important aim of JTAG (Joint Test Action Group) for the development of Boundary Scan in the period from 1985 till 1988. The result obtained is IEEE standard 1149.1 defining a standard test interface.

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As sketched in figure 15.55, the Boundary Scan (BS) of a chip is essentially a shift register which can be used to apply serially a test pattern to primary inputs and to observe serially primary outputs. Thus there is a large similarity to a Scan Path. However, instead, to improve controllability and observability of internal flip flops a BS is used to control and observe the pads of a chip. For a BS there are four additional pads which are denoted as Test Access Port (TAP). TDI (testdata_in) and TDO (testdata_out) are used for serial input and output of data and input TCLK (test_clock) serves for the clock supply of BS. Finally, the input TMS (test_mode_select) is used to select between several modes of operations.

Figure 15.56 demonstrates how to connect the BS pads of several chips on a board so that the Boundary Scans of all chips are combined to create a Boundary Scan of the complete board.

Basically the following applications are possible.

• Test a chip within a larger system (in system verification). Thereby the Boundary Scan is used to apply serially test patterns to the chip using input TDI and to output serially the ob- tained results to TDO;

• Test the wiring on the board. For this purpose BS data is written to a pad to stimulate a wire and then the same data again is read at other pads into the Boundary Scan;

• Test assembly of a board. In this mode chips can be forced to output their identification number to the Boundary Scan. This way the arrangement of chips within the Boundary Scan can be checked, which kind of chip is inserted at a special location;

• Self-test of chips using signature analysis. For signature analysis (section 15.6.2) one needs feedback shift registers at primary inputs and primary outputs of a circuit. Those registers are used to generate pseudo-random test patterns at primary inputs and to compute signatures at outputs. If, anyway, a chip is equipped with a Boundary Scan the BS cells can also be used for self-test, such that less additional hardware is required;

• Combination with Scan Path. If on a chip a Boundary Scan is available then an internal Scan Path may be integrated into the Boundary Scan such that for test mode internal flip flops also become accessible via TDI and TDO. This way additional pads for the Scan Path can be avoided.

To accelerate sequential input and output over the Boundary Scan it is desirable to include only currently relevant chips into the Boundary Scan of a system. Therefore there is a BYPASS mode to replace the Boundary Scan register of a chip by only one shift register cell. In the example given in figure 15.57 five of six chips on a board are in BYPASS mode, such that only the pads of one chip are included in the Boundary Scan.

In addition to the obligatory Boundary Scan register and the bypass register of length 1 there may be other optional registers for special applications. By a multiplexer one of these registers is selected to become the data register (DR) of the Boundary Scan Path. This selection depends on the content of a special instruction register described in section 15.7.2.

From the applications sketched it can be seen that Boundary Scans are mainly introduced to detect faults at board level or even system level. But there

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are also advantages for chip tests when a Scan Path or signature analysis is combined with a Boundary Scan. Furthermore, the BS technique can also be used to improve the testability of a circuit by using an internal Boundary Scan to partition the circuit into several sub-circuits that can be tested separately.

Boundary Scan Cells

There are several kinds of cells used for input pads, output pads, tristate pads, and clock pads within a Boundary Scan. As an example figure 15.58 gives a cell for an output pad. During normal operation mode the circuit output y is written to the pad ‘y_Pad’.

Alternatively, signal y of the circuit can be trans- mitted into the data register (DR) of the Boundary Scan to be written serially to TDO. Furthermore, it is possible to transfer data serially from TDI into the data register and to write that data to the output pad instead of y.

The signal shift_DR is used to determine whether the data register (DR) is loaded serially or in par- allel. Anyway, loading is performed at the rising edge of clock_DR. In the case of shift_DR = 0 the data comes from signal y, otherwise it comes from the previous BS cell via serial_in.

The signal update_DR is used to transfer data from the data register into the second flip flop such that it can be applied to the pad. Because of this

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Master/Slave mechanism the pad signal is changed only after the data register has completely been updated by its serial input. Thus no undefined intermediate values are applied to pads.

The Boundary Scan cell for an input pad looks exactly the same (figure 15.59). Here, alternatively a pad signal or the content of the data register is applied to the primary input x or to the circuit.

TAP Controller

For configuring the Boundary Scan of a chip there is a TAP controller. That is a finite state machine deriving control signals for Boundary Scan cells and which can be used to select the mode of op- eration. Figure 15.60 gives the state diagram of a TAP controller. Its clock signal is TCLK and signal TMS (test_mode_select) is used as input of the automaton.

The state Test Logic Reset is a reset state of the automaton used to initialize the test hardware. This state can always be reached by forcing the input signal TMS to the value ‘1’ for five clock cycles. The function of state Run Test/Idle depends on the current command in the instruction register and may be used for example to start a self-test of the chip (RUNBIST mode) or to put any register data like an identification number on the BS.

In the following the other states shall be explained using the example of a chip test (INTEST mode) sequentially reading the current data from the data register and applying the next test pattern.

Starting at reset state one reaches state Capture DR using input TMS = 010. This state is used for a parallel loading of the data register. This way the output signals of the circuit and the current external signals at input pads are written into the data register with the rising edge of the signal TCLK.

Then for a data register of length k the input TMS is set to ‘0’ for k clock periods such that in the state Shift DR the current content is written sequentially to TDO and simultaneously the next test pattern is read from TDI.

After this, using input TMS = 11 one reaches the state Update DR applying the new content of the data register to the primary inputs of the circuit,

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resp., to the output pads, with the falling edge of TCLK. Finally, with TMS = 10 one again reaches the state Capture DR for the next observation of data and to insert another test pattern.

In addition to the data register there is also an instruction register for determining the operation mode of the Boundary Scan. According to the state diagram of the TAP controller the states capture IR, shift IR, and update IR are used to reload sequentially the instruction register by TDI. The length of the instruction register is at least 2 bits and, depending on the number of implemented operation modes, may be larger. According to the standard, the intended instructions are BY- PASS, EXTEST, and SAMPLE/PRELOAD. The already explained INTEST mode for chip test is optional.

In BYPASS mode the Boundary Scan register is replaced by one single shift register cell. The EXTEST mode, for example, can be used to test the wiring of a board. For that purpose data from the Boundary Scan is written to output pads and again is read into the Boundary Scan at other input pads. With the optional INTEST mode for testing chips, data from the Boundary Scan is applied to primary inputs and data from the primary outputs are trans fered to the Boundary Scan. Thus the only difference between EXTEST mode and INTEST mode is to test external or internal hardware of a chip.

SAMPLE/PRELOAD mode has a special mean- ing. It can be used to take a snapshot of current pad signals by copying all pad data into the BS. Later on that data may be sequentially written to TDO without disturbing the normal operation of the chip. On the other hand, this mode can also be used to reload sequentially the BS with data to prepare a later usage by EXTEST or INTEST mode. Additional modes can be implemented, for example, to temporary include an internal Scan Path in the Boundary Scan such that the internal flip flops of the chip can be observed and controlled by the Boundary Scan.

A quite different application of a Boundary Scan is presented in [15.14]. Here the BS cells are extended in such a way that for a special mode they represent a linear field of automata. Then at every clock cycle a machine state depends on the states of adjacent cells, thus creating a pseudo-random sequence of test patterns, which in addition to the primary inputs can also be applied to the Scan Path.

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