Circuit Verification:Detection of Critical Signals.

Detection of Critical Signals

Whenever possible, circuits should be designed in such a way that slight changes of delays of gates or wires do not affect the logical correctness of signals. A simple example demonstrating a critical timing is shown in figure 9.6.

Circuit Verification-0100

The latch transfers its input data D to output Q as long as input enable is 1. On changing enable from 1 to 0 the most recent input value remains stored in the latch. A problem arises if with the change of enable there is also a change of input D. In this case the state of the latch becomes undefined. In the example the output y strongly depends on the exact signal delays on the paths from b to D and from b to EN. For inputs a = 1 and c = 0 it is undefined whether a value 1 or 0 will be stored in the latch after changing the signal b from 1 to 0.

Circuit Verification-0101

A similar effect can occur if several signals are changing simultaneously, such that for a very short time an incorrect signal (hazard) is generated. For example, if both inputs a = 0 and b = 1 of an AND gate simultaneously are changed to a = 1 and b = 0 then the output will be 0 before and after switching, but for a short time as a result of different delays of the input signals we might obtain y = 1. This timing is sketched in figure 9.7.

If the critical signal y is used to asynchronously set or reset a flip-flop this might produce a wrong stable state of other signals.

To detect such effects one can perform a delay independent simulation. That is an event driven simulation without considering delays in which a signal change from 0 to 1 or from 1 to 0 is simulated by interposing an intermediate state X.

For example, a sequence 01 of signals is replaced by 0X1. This simultaneously describes a slow switching 001 and a fast switching 011. The delay independent simulator propagates X-values until a stable state of the circuit is reached. Only after this  are the new values of signals used for a second simulation step. Whenever a delay-independent simulation reaches a well defined stable state of the circuit can we conclude that indeed in practice the same stable state will be reached by the circuit. In particular, that state does not depend on the exact delay of signals.

On the other hand, if there are undefined signals left after a complete simulation step we can conclude that the logical behavior of the circuit depends on the exact delay of signals. Thus the circuit might be sensitive to fluctuations of manufacturing parameters or to environmental influences. In the worst case this may result in incorrect outputs, and if there are feed back loops the circuit may even oscillate.

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