Mixed Signal Simulation:Application

Application

First example: CMOS Ring Oscillator

In this paragraph a ‘ring oscillator’ simulation at the transistor and logic levels will be discussed.

Ring oscillators often are used as oscillators with electronically controlled frequency. In addition they are used for the experimental test of gate delay times.

Figure 12.10 shows a five-stage ring oscillator, the simple stages of which are formed by NAND gates used as inverters.

The output of one stage is connected to all inputs of the next stage. The capacitor C1 takes care of a reliable start of the oscillation after Vdd is applied. The oscillation frequency is determined by

where n is the number of stages and tr, tf are the rise and fall time, respectively. These times, and with them the frequency can be altered by variation of VDD. The capacitive load formed by the wiring in not shown in fig. 12.10. The oscillation frequency can be lowered considerably by this load. The technological background is again 0.5 μm CMOS technology. The transistors are defined by a SPICE MOS model (LEVEL = 3) [12.1]. The geometry relation W/L was chosen as 10 for the NMOS and as 30 for the PMOS transistors.

The simulated voltages at the nodes ‘in’ and ‘a1’ are shown in fig. 12.11. The switching behaviour is determined by threshold voltages of 1 V and 4 V. With VDD = 5 V the rise time is tr = 50 ps and the fall time is tf = 100 ps measured between the threshold voltages mentioned above. Equation (12.1) gives a frequency f = 1.33 GHz which corresponds well with the simulated frequency of 1.4 GHz.

If lower oscillation frequencies are required either the gate outputs can be loaded capacitively or the number of stages can be increased.

The power supply voltage VDD has a great influence on the oscillation frequency as can be seen from

fig. 12.12. The tuning characteristic of the frequency as a function of VDD is nearly linear, a fact which enables the ring oscillator to be used as a VCO (voltage controlled oscillator). The oscillator frequency is highly dependent on the temperature, therefore the oscillator is hardly usable without being embedded in a controlling PLL circuit.

The modeling of the ring oscillator at transistor level has the advantage that several influences can be studied, e.g., those of VDD, temperature, or capacitive loading.

The effort with respect to simulation time is more than ten times as great as with a simulation of a logic level ring oscillator model, which is shown in fig. 12.13. The fundamental structure of coupled NAND gates is identical to the one shown in fig.

12.10. The stimulus at the input of gate ‘Ux1A’ is only necessary for a guaranteed start of the oscillation. As expected, the logical circuit also generates an oscillator signal, but the frequency is different from that found with the circuit in fig. 12.10. In order to produce results which are sufficiently precise at logic level the NAND model from fig.

12.7 has to be improved considerably. The timing model ‘D_MyGate’ has to be extended in order to cover influences of VDD and temperature. In the case of a ring oscillator a small but critical circuit it is advisable to do the modeling at the transistor level.

12.4.2 Second Example: Phase Lock Loop (PLL)

The simulation of a PLL discussed in this paragraph is an example for a mixed signal simulation with components defined at different levels of abstraction. The reason for this lies, on one the hand,

in the different nature of the components and, on the other hand, in the degree of going into details of the different circuit blocks. By means of a PLL a VCO is locked to a reference oscillator with respect to frequency and phase. The most important applications for a PLL are to be found in the fields   The PLL circuit discussed here is shown in fig.

The VCO which is realized by the ring oscillator discussed in the previous paragraph (fig. is controlled with respect to its frequency via its power supply voltage. This component is described on the transistor level. The oscillator  signal is directed via a buffer to a frequency divider. The purpose of the buffer is, on the one hand, to decouple the ring oscillator from the frequency divider. On the other hand, the buffer  ring oscillator to the logic values of the frequency divider because a change in the control voltage of the VCO not only changes the output frequency but also the output voltage amplitude. Without this adaptation the frequency divider which is modeled at the logic level could produce undefined states. The buffer is modeled partly at transistor, partly at logic level. The frequency divider consists of three slope controlled D flip flops and divides by a factor of eight. At the beginning of the simulation the flipflops are reset.

The digital phase detector modeled at the logic level compares frequency and phase of the divided VCO signal with those of a reference signal which The following parameter values were used for the simulation of the PLL shown in fig. 12.14: KVCO = 2π · 300 MHz/V, KD = 2/π V and KAmp = 1, τ1 = 50 ns, τ2 = 10 ns.

is provided in the form of a digital stimulus.

The output of the phase detector is smoothed by an analog passive loop filter. The following amplifier is described as an analog behavioral model, i.e., a simple voltage controlled voltage source. The actual design of the amplifier has to be done in a later  stage of development. The dynamic properties of the PLL, important for the transient and locking behavior, are described by a few characteristic constants only [12.9].

The natural frequency ω n of the PLL is deter- mined by:

With these values the natural frequency fn = 8 MHz and the damping factor ζ = 0.3.

The simulation result for a reference signal with a period of 8 ns is shown in fig. 12.15 with an end time of 200 ns. The derivable values for fn and ζ correspond well with the calculated values above.

The PLL is an example of a so called ‘stiff system’ in which the time constants involved lie widely apart. The frequency of the VCO is usually at least two orders of magnitude greater than the natural frequency of the PLL. The time step of the simulation is determined by the smallest time constant, the duration of the simulation by the largest time constant. This leads to simulation with many steps, therefore here it is of special importance that the computer time needed to perform a single step is minimized. This is accomplished in the example just discussed because decisive parts of the system are modeled at the logic level.