EDA Tutorial:Place and Route in a Standard Cell Design Style

Place and Route in a Standard Cell Design Style

In the design of FPGA circuits, after the synthesis of the EDIF files, the compiling and programming of the FPGA device, everything is defined and the component is completely configured. With ASIC designs, there are two possible scenarios:

• Delivery of the design to an ASIC provider in the form of a so called simulated netlist (EDIF);

• Place and Route of the design with one’s own tools, verification of the results, and delivering of the design as a geometrically exact GDS II File.

For similar designs in industry the netlist version is frequently chosen, but here the second scenario which includes the backend processing, the phys- ical design, will be demonstrated in more detail. This needs special software tools, which allow the mask design at the lowest geometry level, and tools for checking the generated geometries against the predefined design rules (Design Rule Check, DRC), and allow one to extract parasitics

and electrical connections (XTRACT, CALIBRE). These tools are integrated in complex software systems, e.g., IC station (Mentor Graphics) or similar from other EDA providers. Because of the high investment needed for these programs, as well as the investment in personal skills in using these tools, such programs are only available at special design houses, universities, or companies engaged in analogue or huge mixed signal IC designs.

The following description demonstrates the steps with Mentor IC station which was installed at the site of the author. The technology used is a fairly old 2 metal layer CMOS technology (ALCATEL MIETEC 0.7). Newer technologies may be used in the same way with more metal layers (up to 6 are usual today), and a channel-less routing style which allows high density function blocks may be adapted. For the small ‘rolling dice’ example such a high resolution technology would be wasted, because chip size is determined by the number of pad cells, a further miniaturisation of the core would not save any silicon area (so called pad limited design).

The first steps with using the IC Station are:

• Loading of the process file, which describes the technology;

• Loading of the cell library of the target technology;

• Loading the netlist of the logic which has to be processed.

From the netlist and the geometry of the cells the program generates a floor plan automatically, containing rows for the possible placement of the cells. The length of the rows, which are ordered in a rectangle, considers the number of cells used plus some extent of about 10 %. This floor plan may be edited with the graphical tools, rows may be moved, inserted, or deleted, rows may be mirrored or turned. All rows in the core area have the same height as the core cells. For the periphery area the row size is adopted to the larger pad cells, see fig. 26.13.

A few operations now allow to place the standard cells automatically, the pad cells in their predefined way and in their relative position. The core cells are placed using optimal placement algorithms, so that there is a minimum interconnection length.

Figure 26.14 shows placement of the cells for the ‘rolling dice’ example. The interconnections are  shown as overflows, behaving in display like ‘rub- ber bands’. The cells may be moved and replaced interactively, but this normally makes no sense and the generated placement cannot be significantly improved.

In the next step the autorouter is called, which routes all electrical connections between the cell pins in a 2-layer connection structure known as the channel. In a two layer routing the channel lie between the cell rows. The autorouting process consists of several smaller processing steps, the power routing, the course and final routing of the signal interconnects, and at least some improvement step eliminating superfluous vias and complex connections with many bends. These processes run automatically, and in most cases all interconnects are routed. If there are some unrouted signals, which happens if there are too many constraints defined for the autorouter, they may be routed interactively or else the routing step has to be repeated again.

Geometric constraints concerning row distance and channel width make autorouting more difficult. Best results may be achieved if the tool is able to select channel width dynamically and all cells are made slideable on the rows, so channel interconnections may be routed through the gaps between them (so called feed through cells are inserted). The row length should be extended by about 10 % for that to be possible. Later this additional area can be regained by compaction. The result for the ‘rolling dice’ example is in fig.

26.15 after routing and compaction. Compaction is a special processing step at the geometric level, which allows a design to be shrunk to the minimum distances given by the design rules. At the end the design can be marked with a scribe note on the upper metal_2 layer.

In the next step the geometries have to be checked with a DRC tool (Calibre) against the geometry design rules. This program may be part of the IC Station or a stand alone tool (Dracula). It is not unusual that there are several small DRC errors which may be corrected with low effort by hand.

Furthermore a LVS Check has to be performed, comparing the placed instances and the routed interconnections with the netlist. So the existence of all instances and interconnects are validated. This step is carried out without problems if the CBC mode of the IC Station is used (CBC stands for Correct By Construction).

Furthermore a parameter extraction may be per- formed to evaluate the delays of the wire connections. Using back annotation the extracted parasitics may be included in the simulation and so al- low a post layout simulation giving exact data for wire delays. This is very important for deep sub- micron technologies, where wire delay dominates gate delays. For the ‘rolling dice’ design, this is omitted because of the low clock frequency and the 0.7 CMOS technology used.

ufacturer via File Transfer Protocol FTP. In the case described, the chip was manufactured via the prototype multi wafer service of europractice [26.5], the chip photo is shown in fig. 26.16.