Digital Simulation:Digital Simulation: Why?

ICs accommodate millions of transistors in a single device. Therefore it is a necessity to identify faults in the design process at the time when they are implemented. Faults already may have been introduced in the process of specification, in the implementation into digital logic, or even in the models used for simulation of the circuit.

Digital Simulation-0153

In designing digital circuits one of the most important tools for a designer is a simulator. A simulator allows the verification of a circuit (DUT, device under test) after different steps of development at gate level. However, one must be aware that every simulator is based on models. The result of a simulation is only as accurate as the model used.

Apart from verifying the intended function of a digital circuit, the designer must take into account the efficiency of his stimuli for the production test of his circuit. With special programs fault simulation will deliver the fault coverage of a given test program.

In the following we will use the terms functional simulation, pre-layout simulation, post-layout simulation, and fault simulation. Functional simulation applies for the simulation of the logic which the designer uses as source code. After optimizing  the source code pre-layout simulation provides the reaction of the optimized logic. Consequently after mapping the logic to the target device, post-layout simulation enables the designer to simulate the actual logic of the IC used, which may differ from the original logic of the source code, owing to the logic modules available in the specific technology of the target device.

All logic circuits in this chapter have the prerequisite that the design engineer agrees with the goal that his circuit is testable.

Expressed in figures, it would mean that the faultcoverage is about 98 %. This in turn means that testability must be designed from the very beginning of the design phase. Additionally, because of  the multiple chances of faults and the multitude of their effects in a complex circuit, the test pattern for production test must be considered. Only if the circuits produced react correctly to the stimuli will the customer accept the ICs.

Digital Simulation: Why?

One of the main benefits of digital simulation for the development engineer is the verification of his design right from the start of his project. In the following the power of digital simulation is demonstrated by considering the different stages of design process.

Digital simulation for design verification

Independently of the language of the source pro- gram, every circuit in the design project is translated into digital logic, which in turn is implemented in an IC. Digital simulation enables the design engineer to verify the function of his design at every stage. However, he has to provide stimuli to excite the circuit. Digital simulation documents the implemented function of the circuit with the related test pattern.

Digital simulators have to simulate the behavior of every circuit, e.g., a faulty circuit, as closely to reality as possible. In particular, the following faults should show up:

• Unwanted feedback;

• Oscillation;

• Asynchronous circuits;

• Spikes, hazards.

Considering costs, the number of stimuli (test vectors) should be kept as small as possible. The state of the art is to download 200 k test vectors in one process without reloading.

Finally, the designer verifies and documents the function of his circuit using digital simulation.

Fault simulation to proof the effectiveness of stimuli

The development engineer is responsible for the test of his circuit. Therefore, it is necessary to know about the effectiveness of test stimuli. Fault simulation initially was developed for the evaluation of production test patterns. Manufacturing faults were modeled as hard faults. The fault simulator simulates the faulty circuit once for every fault. The result is the number of faults detected by the test stimuli.

With fault simulation it is documented how many of the inserted faults are detected by the test vectors specified. In practice it was shown that the development engineer receives additional information by the fault simulation results, which lead to a deeper understanding of the behavior of the circuit. This in turn may lead to the recognition of development faults. Certainly, fault simulation detects simple faults such as open pins of a circuit. Fault simulation checks some aspects of consistency of the design. One important aspect which fault simulation discovers is which nodes of a circuit do not change their values during the complete testing process. And, as mentioned before, which faults are not detected with the given test vectors. This may be owing to an insufficient number of test vectors or may be a result of lacking testability of the circuit. It may, too, indirectly lead to the recognition of a specific function of the circuit being blocked under specific conditions. Oscillating parts are detected as well (section 11.6).

All development platforms provide specific pro- grams for fault simulation.

Requirements which must be met by the de- sign engineer

Testable digital design demands a systematic hierarchical structure of testable sub-modules. The fault coverage should be around 98 %. To produce an electronic product efficiently the production engineering unit will ask for testable products.

Modules consisting of combinatorial circuits must be constructed to have a fault coverage of 100 %. If this is not possible the modules must at least be reorganized to an appropriate size. With this approach test programs of modules are re-used for testing the complete circuit. Both development time and cost are thus reduced considerably.

The Boundary Scan Test is one approach to allow- ing easy access to internal nodes of a circuit via a serial link. Nodes may be set to specific values. Values of specific nodes can be accessed for further use. The 4 line port used for this purpose is TAP (Test Access Port). IEEE Standard 1149.1 Test Port And Boundary Scan Architecture specifies TAP. There are differences between 1149.1 and the JTAG (Joint Test Action Group) Standard which preceded 1149.1. In spite of additional costs for more complex hardware within an IC, the cost of testing (test vectors, test time) decrease which reduces over all costs considerably.

Integrated Circuits and Simulation Model

Digital simulation uses a model of the circuit which the designer has specified with his source code. This model uses the parameters of the target device. Examples for such parameters are gate delay, specific flip flops of the target technology, or the capacity of interconnections. If a development environment is used, all parameters are stored in a specific library. This parameter library for components is different for distinct brands and depends on specific technologies.

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