EDA Tutorial:Verification by Functional Simulation

Verification by Functional Simulation

Verification is carried out with a digital simulator. The simulation of the schematics may be carried out with Quicksim (Mentor). Increasingly this program is being replaced by modelsim (Exemplar, Mentor Graphics), a VHDL compiler and simulator. To use this simulator with Design Architect the netlist has to be generated in structured VHDL format, and in which the library components have to be taken from a VITAL compliant library.

There is no quality difference in simulating with modelsim as a VHDL simulator and a more symbol oriented classical simulator Quicksim. Delay times of instantiated gates, as far as they are included in the library, are taken into account. Figure 26.7 shows a screenshot of the modelsim simulation of the dice counter FSM, the related stimuli script is contained in list 26.3.

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The building blocks are simulated one after an- other and differences from the intended behaviour have to be modified at the design entry level until the desired performance is reached. Next, the blocks are combined stepwise and their intercommunication again validated by simulation. Lastly, the simulation of the entire design at top level is performed fig. 26.8. The ‘rolling-down’ can be seen in the traces quite clearly.

The top level simulation takes a relatively long time even though this is a really small circuit. This comes from the huge number of cycles required. Because of the timer a minimum of 16 seconds real time must be simulated, mapping to minutes of simulation time on a workstation and delivering 20 Mbytes of data. So simulation at the block level is very important. In the case of VHDL, simulation does not yet include the timing behaviour because synthesis has not yet been done and there is still a behaviour description only.

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