Digital Simulation:Limits of Digital Simulation and Treatment of Complex Circuits.

Limits of Digital Simulation and Treatment of Complex Circuits

To develop ASICs the use of powerful tools is mandatory. So a development engineer may design his circuit step by step and integrate the intermediate results in his software environment. He verifies the design at various levels to identify faults as soon as possible if they occur during the design process. Thus the cost of eliminating faults is minimized.

If digital simulation guarantees that the design is fault-free, it depends on various factors:

• Accuracy of simulation models and the related parameters;

• Quality of test vectors;

• Definition of the function of the circuit.

It is obvious that simulation results depend heavily on the models used.

In the same way the result of a simulation represent the reaction of the circuit to the test vectors defined by the designer. With them he is able to create critical situations for finding out whether the reaction of the circuit is correct.

A difficult task is to define the function of the circuit. For real circuits it is quite impossible to de- scribe the complete function. There is always the danger of overlooking parts of the function which may malfunction because of insufficient definition.

Complex circuits implemented in ASICs, such as controllers with various interfaces are difficult to simulate as a complete circuit. The simulation time can be extremely long. In this case it is advisable to generate code for an FPGA. If the source code is in VHDL the additional effort can be justified. In this case the emulation of the hardware substitutes for the simulation of the complete circuit. Finding de- sign faults may be more difficult in emulation. One advantage of the FPGA is that the circuit’s speed is close to that of an ASIC. For testing, stimuli are applied by a pattern generator. A logic analyzer and oscilloscope help to evaluate the reaction of the circuit. Additionally, the real environment can be used as a test bed for the hardware (fig. 11.47).

Digital Simulation-0207

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