Programmable Logic Devices:Programming of PLDs

Programming of PLDs

Programming means the implementation of a de- sired function in the selected target hardware. For this purpose signal connections which are not required have to be interrupted and/or the necessary signal connections have to be realized. This will be illustrated by the GAL 16V8.

Programming of the GAL 16V8

The GAL 16V8 offers in its logic diagram according to fig. 18.23 a programmable AND matrix with 2 × 16 inputs and 8 × 8 AND terms. These 2048 crossings must be addressed individually in order to be able to interrupt the connection. In addition to this further programming positions define the desired architecture of the output cells.

The GAL 16V8 offers an integrated selection logic to address the total of 2196 programming positions. This logic has to be driven with the existing pins. For programming purposes the pins necessarily have another task, as is shown in fig. 18.25.

Programmable Logic Devices-0086

First, the programming data are latched to a shift register via the serial data input (SDIN). Each position of the shift register is allocated to an AND term (product term, PT). The row address (RAG5 to RAG0) indicates the input within the AND terms. Figure 18.26 shows the row address map block diagram.

Only 36 different row addresses are used:

• RA0 to RA31 cover the AND matrix area;

• RA 32 receives the ‘electronic signature’, e.g., a field with 64 bits for arbitrary user data such as circuit name, version identification or inventory identification;

• RA 60 is used for the definition of the architecture of the output cell; and

• RA 61 is for the security cell. It provides a copying protection against unauthorized readout of programming data. After being programmed it does not allow access to the AND matrix area;

• RA 63 drives the erase cell. Its programming releases a complete bulk erase. The component is afterwards in the original state again.

A programming voltage of approximately 16.5 V at pin EDIT puts the GAL 16V8 in its program- ming mode. With each clock at SCLK the shift register accepts the new value at SDIN. A clock  pulse of the length of 10 ms at pin /STR starts the actual programming. The signal P/V changes from programming mode to verification mode. For control purposes the state of any programming position can be read out at SDOUT by means of the shift register.

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The attempt to program the GAL 16V8 with simple laboratory means such as power supplies and switches is obviously doomed to failure. Better computer supported tools are needed.

Computer Support for Programming
Starting from the design input (see chapters 3 to 8) three steps lead to the programmed logic device:

• First of all, the circuit specification has to be transferred to rather simple logical relations between the input signals and the output signals. Moreover, the polarity, and if necessary, a storage element has to be selected. This equation is still independent with respect to realization.

• In the second step the equations are harmonized with the resources of the chosen component. The × marks in the logic diagram (Fuse Plot) promise a success and represent the programming instruction.

• The actual programming is carried out by a programming unit, e.g., the programmer. It transmits the programming data to the logic component and supplies the required voltage pulses.

As promised, the variable divider mentioned in section 18.3.2 shall be taken as an example to demonstrate these steps. The listing in 18.1 shows the design input with the names of the input signals and output signals, their relationship in form of Boolean equations and the desired pin allocation. The sign ‘:=’ assigns the value of the logic operation to a storage element, the sign ‘&’ represents the wired AND.

Programmable Logic Devices-0088Programmable Logic Devices-0089

Each line in list 18.2 requires an AND term for its realization. A maximum of three AND terms, which are wired OR, is necessary for each output. This is therefore the Sum of Products which is supported by the target component GAL 16V8.

The second step, namely, the adaptation to the resources of the logic component, does not require any transformation of the equations found. List 18.3 only shows the necessary AND terms of the logic diagram with the × marks of the still functioning

Programmable Logic Devices-0090Programmable Logic Devices-0091

The JEDEC Form

The last step, e.g., the transmission of the programming specification into the target component is realized by the programmer. This is a variable voltage generator and analyser for a great number of pins which are contacted via a ZIF adapter (Zero Insertion Force). The programmer receives the programming data in the international standard JEDEC form (Joint Electron Device Engineering Council).

This ensures the understanding between arbitrary computers and programmers. The list 18.4 shows the programming data of the given example in the JEDEC form.

Programmable Logic Devices-0092Programmable Logic Devices-0093

All information given prior to the first ‘*’ are comments for the operator of the programmer. The actual programming data starting with a characteristic letter are followed by numbers and are finished by ‘*’:

• D represents DEVICE and it opens the field of the component code. It also allows the programmer to control whether the proper component has been used;

• G represents GUARD applies for security cell (not programmed in the example given);

• QP represents QUANTITY of Pins indicates the number of pins; and

• QF represents QUANTITY of Fuses indicates the number of programming positions;

• F indicates the ‘DeFault’ value for the programming positions which are not listed;

• L for LINK defines the desired connection state (1 means interruption, 0 keeps the connection in tact) starting from the indicated starting address;

• C for Checksum presents the 4 digits of the check sum.

The addresses of the programming positions are realized by mere consecutive numbering from left to right and from top to bottom, as shown in fig.

18.23. Such a clear allocation allows the conversion of the two-dimensional ‘fuse plot’ according to list 18.3 into the one-dimensional JEDEC file in list 18.4. The × marks are replaced by ‘low  (0)’ and the minus signs are replaced by ‘high (1)’.

Knowing this and knowing the pin allocation the path can also be traced back; the JEDEC file results in a ‘fuse plot’, revealing the Boolean equations. Thus a JEDEC file can also be accepted by a logic simulator.

After receipt of an error-free complete JEDEC file by the programmer, it will find in its archive, amongst its component codes, the exact voltage values and pulse widths for the programming of the component. This information is missing in today’s data sheets, recommending programmers instead.

Only manufacturers of programming devices (see section 18.6) are furnished by the semiconductor companies with their respective latest data. This guarantees a careful and yet long lasting programming.

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