Design for Testability:Fault Models

Fault Models

Fault models specify which kinds of faults have to be detected by a test. Often one uses structural models where faults are equivalent to a structural modification of the circuit. The most well known example is the model of ‘stuck at’ faults. In that model a fault causes the signal of a wire to be fixed at the value 0 or at the value 1.

Such structural fault models are very abstract representations of physical defects occurring during chip manufacture. For example, it does not matter whether a stuck at fault is caused by a short between a wire and a supply line or by a line interruption. Instead of directly detecting a physical defect, one tries to observe its effect on the circuit behavior. Whenever a defect has an effect other than described by the fault model it will not be detected using the model.

The quality of a fault model can be defined by the number of faults covered. Since more thorough fault models need higher test effort, because more possible faults have to be considered, a trade off between quality and cost of a test must be found

in practice. For that reason one often tests only for some limited percentage of the faults (98 %) described by the fault model. This percentage is called fault coverage of the test.

Since fault models represent simplifications and not all possible defects of a chip are covered, a high fault coverage does not necessarily corre- spond to a high defect coverage. Therefore even after successfully applying a complete test with fault coverage of 100 % one can not be sure that the tested chips actually operate correctly for all possible inputs.

Depending upon the fault model used different sets of test patterns are needed. In order to achieve a good defect coverage one can, for example, gen- erate test samples for a fault model A until a good fault coverage is also achieved for another model B. In this case one can hope that the produced test patterns are generally well suited and do not cover only a special type of faults.

Stuck at Faults

The single stuck at fault model defines as only possible a fault which at the gate level of a circuit fixes exactly one wire α to value 0 or to value 1.

This is called an α stuck at 0 or an α stuck at 1 fault.

Figure 15.4 shows an example of a circuit such that wire α is permanently fixed to 0. This fault can only be observed if one tries to set wire α to 1. This is called the stimulation of the fault. In the example the fault can be stimulated by b = 1. Furthermore, the primary inputs of the circuit have to be set so that the faulty behavior can also be observed at a primary output. Thus the fault has to be propagated from the fault location α to a primary output. In the example it is only by a = 1 that we can propagate the fault through the upper AND gate. Otherwise for a = 0 we would obtain γ = 0 for the correct circuit and also for the faulty circuit. Accordingly we also need c = 0 to observe the fault at output y. Thus for the input pattern (a, b, c) = (1, 1, 0) the fault α s a 0 is stimulated and propagated to output y. In this case the input is a suitable test pattern for detecting the fault.

Since for the single stuck at fault model exactly one wire is stuck to a specific logic value, the model describes exactly 2 × m possible faults for a circuit with m wire segments. A complete test has to detect every such fault.

In counting wire segments special attention has to be paid to multi-terminal nets. For example, in the circuit shown in figure 15.4 there is a branching node transmitting signal b over wire segments α and β to two gates. A fault at location α does not affect wire segments b and β . Thus for a better understanding branching nodes should be considered as special gates transmitting an input signal to several outputs, as shown in figure 15.5. Then obviously in the example circuit there are eight wire segments (a, b, c, α , β , γ , δ and y) and the single stuck at fault model consists of 2×8 = 16 possible faults.

With the special treatment of multi-terminal nets frequently occurring interruptions of wire segments can be handled. An interruption of the wire segment b has effects on signals α and β , but an interruption at α has no effect on b and β .

An extension of the fault model considered is the multi stuck at fault model also considering stuck at faults on several wires at the same time. For example the combination (a s-a-0, b s-a-1) is a possible fault within this model. With m wires and two possible faults per wire there are 4×[m×(m−1)]/2! possible double faults, 8×[m×(m−1)×(m−2)]/3! possible triple faults, and, finally, 3m − 1 possible multiple faults. Of course the model of multiple faults is more thorough because it contains many more faults than the single fault model. However, it is not clear whether the increased test effort substantially improves defect coverage.

Cellular Fault Model

For the cellular fault model one assumes that a gate has a wrong combinatorial behavior. As an example table 15.2 describes the logical behavior of a NAND gate. A possible cellular fault might be a faulty entry within the table. Then in the example indicated the NAND gate would behave like an XOR gate. Of course, this modification does not correspond to a realistic defect. As an interesting property of the cellular fault model please note that every single stuck at fault is also a cellular fault. Thus the cellular fault model is a real extension of the stuck at fault model.

In order to stimulate all possible cellular faults one obviously has to drive every gate with all possible input combinations. As a consequence substantially more test patterns are needed than for the stuck at fault model. In figure 15.6 this is demonstrated by a very simple example. Though a complete test for stuck at faults consists of only four test patterns, a complete test for cellular faults needs six test patterns. All test patterns are given in table 15.3.

The fault model of bridging faults considers short circuits between two wires α and β of a circuit (figure 15.7). As long as both wires represent the same logic value the fault has no effect. However, a short circuit between signal 0 and signal 1 may change both signals to 0. This is called an AND bridging fault because the resulting faulty signal can be obtained by an AND operation. If on the other hand the resulting signal is 1 we have an OR bridging fault. Figure 15.8 shows the modeling of an OR bridging fault.

To stimulate the fault one assigns different logic values to wires α and β obtaining a change of α t or β t in the event of a fault. To observe the fault the signal modification has to be propagated to a primary output. However, observing the fault becomes more difficult if it causes a feedback within the circuit. Then for an extreme case the circuit might oscillate.

For a circuit consisting of m wires there are m×(m−1) possible pairs of wires for short circuits.

Thus the fault model of bridging faults describes a quadratic number of possible faults. In practice one often restricts the fault model to short circuits between adjacent wires of a layout. However, this presupposes that in addition to a netlist geometrical layout data is also available.

Also for bridging faults there are several exten- sions of the fault model. For example, shorts between three or more wires may be considered. Another extension is the weak bridging fault con- sidered in section 15.3.4. A further aspect of bridging faults will be discussed in more detail in section 15.8 in connection with the method of IDDQ tests. Since short circuits produce a faulty current, such faults can also be detected because of an increased power consumption of the chip instead of observing output signals.

Parametric Faults

In addition to the hard bridging fault described in section 15.3.3 as a short circuit between wires, there are also weak bridging faults coupling two wires by a resistance, as shown in figure 15.9.

Here the circuit behavior depends strongly on the strength of the faulty resistance and may vary with the kind of physical defect. Opposite to structural faults, such faults are called parametric faults.

For the extreme case of R = 0 Ohm we have a hard bridging fault, and in the other extreme of R → ∞ Ohm the circuit is correct. For other resistances the signal values obtained may not be well defined, so that a signal may be interpreted as logic 0 by one gate and as logic 1 by another. Such faults are hard to detect. It may even happen that the logical behavior of the circuit is correct but that there is a slight increase of power consumption. In this case the fault is classified as an IDDQ fault. Such faults are described in more detail in section 15.8.

Another effect of weak bridging faults may be an increased gate delay. This time the fault is called gate delay fault.

Accordingly one speaks of path delay faults if over a long path through the circuit we obtain an increased signal delay. Eventually individual gate delays are still acceptable; however, altogether they add up to a large path delay such that for high clock rates the circuit may produce incorrect results. Obviously in this case the fault can be observed but cannot clearly be localized within the circuit.

Transistor Faults

Depending on the level of abstraction of a circuit description different kinds of faults can be formulated. Refining a circuit from gate level to transistor level additional gate internal wires become visible and can be included into the fault model. Because of stuck at faults at the gate connection of a transistor the transistor may permanently be on or permanently be open. In these cases the faults  are called stuck on fault and stuck open fault. Figure 15.10 gives an example of such a transistor fault in a CMOS implementation of a NAND gate.

The fault ‘T3 stuck open’ causes transistor T3 never to be conducting. This corresponds to a ‘stuck at 0’ at the gate of T3. As a consequence using input a = 1 and b = 1 output y of the NAND gate is not connected to VDD neither to VSS. Then y is an isolated node and for a certain time the node will maintain the last valid signal value. Thus the behavior of the faulty NAND gate becomes sequential, so that it behaves like a dynamic memory cell. If the stored value coincidentally corresponds to the intended value the fault will not yet become apparent.

In the case of stuck on faults the circuit behavior is quite different. Such a fault can dynamically generate an undesired path from VDD to VSS drastically increasing the quiescent current. For example, the fault ‘T3 stuck on’ in a NAND gate would create such a path for input a = 0 and b = 1 (figure 15.11).

Depending on the sizing of the transistors involved the path behaves like a voltage divider, and in spite of the fault the output y may obtain the correct logic value. In this case the fault cannot be detected by observing primary outputs but only by a current measurement. For the other extreme case the faulty path may result in a very high current flow, such that the chip immediately will be destroyed and the fault becomes obvious