Circuit Verification:Statical Analysis of Timing

Statical Analysis of Timing

Typically for logic synthesis the designer has to specify the desired clock rate, and after synthesis he has to check the generated critical paths in order to see whether the given timing constraints are actually satisfied. Those critical paths are calculated during synthesis using a statical analysis of timing. For this all paths within the circuit are checked for the worst case delay times of changing signals. The critical path found then defines the fastest possible clock rate for which the circuit is able to derive correct outputs.

Example: In figure 9.5 changes of signals are generated at primary inputs and at the outputs of flip flops. They are propagated through the circuit to the inputs of flip flops and to primary outputs. For example, there is a path from output Q of flip flop s1 to input D of flip flop s3. On this path there is only one NOR gate. In table 9.1 the relevant delay times and capacities of NOR gates are given as an example. In general the delay of output y owed to a rising edge at input xi can be computed by

Circuit Verification-0097

Here cy denotes the capacity to be driven by Signal y. As shown in the table, a rising edge at input x2 causes a modification of the output signal y after a delay of typically 0.12 ns. On the assumption that the other input x1 of the NOR gate is 0, a falling edge is generated at y. Furthermore, since the signal produced has to drive two inputs of gates (s3 and g2) each of 0.04 pF, we obtain a total signal delay of 0.12 ns + (0.5 + 0.04 + 0.04) · 1.02 = 0.73 ns from input x2 of the NOR gate to input D of flip flop s3, neglecting the capacities of the interconnections. In total we obtain a signal prop-

Circuit Verification-0098Circuit Verification-0099

With similar calculations we find a critical path running from Qs1 to Ds4, as emphasized in figure 9.5. It limits the maximal possible clock rate of the circuit. If necessary, the time performance  of the circuit may be improved by re-timing. This means reallocating the combinatorial parts of the circuit to the paths between flip flops.

straints given by the designer. For example, the designer might state that a primary input a will not be stable before 2 ns after the rising edge of the clock signal. Furthermore, it may be required that the primary output y must already be stable at 3 ns after the rising clock edge and should be able to drive some pre-defined capacityance. Any determined deviations from such requirements can be used to control synthesis.

The timing verification problem consists of checking whether the desired timing is still valid after generation of the layout, that is, after per- forming placement of cells and after routing wires. A possible approach of timing verification is to simulate the circuit considering also capacities and resistances of wires that are extracted from the layout. This would be called a dynamical timing analysis. As previously mentioned, this method is very time consuming because too many stimuli have to be considered. Also it does not help to restrict the simulation to critical signals found during logic synthesis, because there may exist different critical paths after routing.

Therefore, as a more efficient alternative one should perform a static timing analysis for the netlist extracted from the layout considering also real capacities and resistances of wires. Again, the more precise signal delays obtained on all paths have to be compared to the timing constraints specified by the designer. Whenever a path does not satisfy the required timing one can try to repeat the synthesis using more restrictive timing constraints for that critical path.

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