Mixed Signal Simulation:Concepts of Mixed Signal Simulators.

Concepts of Mixed Signal Simulators

Requirements and Course of Simulation

A simulator for a mixed signal application has, on the one hand, to take care of modeling and signal description at all levels of abstraction. On the other hand, it must be possible to simulate all circuit blocks simultaneously. For this purpose it is necessary to arrange signal exchange and signal conversion between the different levels of abstraction.

In order to couple the different levels of abstraction one needs interfaces, as shown in fig. 12.1. The interface programs mainly have the task of maping the different forms of signals of the different levels of abstraction to each other [12.5].

Discussing the transfer between system level, RTL, and logic level, mapping means in practice a re- grouping of signals. A common feature of the signals of the three levels mentioned above is that they are of the type ‘Boolean’. A ‘word’ has thus  to be resolved into ‘bits’ when transferring from RTL to logic level.

Discussing the transfer between transistor and logic level, mapping becomes more difficult as the example in fig. 12.2 shows. The analog voltage VY1 is mapped to the logical value Y2 by means of the interface ADC. For this purpose the infinite number of analog voltage values is assigned to the three possible logical values ‘0’, ‘X’, ‘1’ by comparing them with the threshold voltages Vth0 and Vth1. The logical block in fig. 12.2 is simply an inverter which inverts the logical signal Y2 into Y3. The following interface DAC maps Y3 to the analog voltage Vy4. There the difficulty is to map the finite number of logical values to the infinite number of analog voltage values. There is found a stepped function for VY4 whereas a real inverter would show a ramp function for VY4.

Figure 12.3 shows the course of a mixed signal simulation in which, as an example, transistor and logic level connection is discussed. The total circuit is separated by the simulator (perhaps with user support) into sub-circuits each of which comprise only one level of abstraction. In addition to the circuit description the user has to input analog and digital stimuli and commands referring to simulation nature and size. The simulation starts with the calculation of the initial values at the inner nodes and at the interfaces. All following program steps are performed within a loop which is passed through in a so called minimum resolvable time (MRT) [12.6].

In the first block of the loop in fig. 12.3 an analog simulator calculates all voltage values at the analog nodes. Those analog nodes which are connected to logic nodes (in the original circuit diagram) feed a voltage value to an AD interface. The AD interface maps the analog voltage values to logic values. There follows a logic simulation in which the logic values for all logic nodes are calculated, taking

into account the logic values delivered by the AD interface. The logic nodes which are connected to analog nodes (in the original circuit diagram) feed the calculated logical values to a DA interface which forms the respective analog voltages. At the end of an MRT step are found the output voltages or logical values at analog or logical nodes, respectively.

If the given simulation time is over, the simulation will be terminated, otherwise the next MRT step will be performed in which the results of the previous step and possible new stimuli are taken into account.

The mixed signal simulators which are currently in use fulfill the requirements mentioned above with two different approaches:

• one group of simulators uses a separate simulation program for each level of abstraction and the communication is carried out by means of an interface program (example: Continuum of Mentor Graphics).

• another group of simulators covers all levels of abstraction in one comprehensive simulator which comprises all necessary models, signal descriptions, and algorithms (examples: PSPICE, VHDL-AMS).

In a recent publication a new comprehensive simulator is presented which supports the separation of a circuit with respect to different levels of abstraction [12.7].

Separate Simulators

In this approach a separate simulator is used for each level of abstraction. The single simulators are coupled by means of interface programs and a co-ordination program. Generally this program has a graphical user interface which enables the user to input the circuit description with the simulation control and to organise the output of the results. The co-ordination program also performs  the overall control of the separate simulators. This approach is suitable for systems with clearly de- fined circuit blocks which can be assigned to the different levels of abstraction like in fig. 12.4. Typically these circuit blocks are rather large. The connection between the blocks is formed by many different signals. The approach with separate simulators has several advantages, e.g., the simulation within one level of abstraction can be performed with simulators which are existent and reliable.

In this way it is also possible to simulate systems which comprise more than two levels of abstraction, provided that the necessary simulators are available. For example, an analog simulator could be used for the transistor level, a logic simulator for  the logic level, and the VHDL simulator for RTL. As mentioned above, an example of this approach is the program Continuum of Mentor Graphics.

Comprehensive Simulator (Example: PSPICE)

In this approach all levels of abstraction which exist in a certain system are covered by one simulator only. The simulator also comprises interfaces in order to map the different signal types of the different levels of abstraction to each other. This approach is especially successful if the levels of abstraction are strongly intertwined, as is the case in fig. 12.5. Here the single blocks are relatively small and there are multiple connections between the blocks. The approach with a comprehensive simulator is efficient when dealing with small systems with intertwined levels of abstraction. The overhead for changing simulators is not necessary, which is a decisive advantage when dealing with small systems.

The following paragraph discusses PSPICE as an example of a comprehensive simulator. The components of the logic level are described as time models (for delay times) and as I/O models (for input/output properties). If the digital component has connection to analog components automatically AD or DA interfaces, respectively, are inserted, the models of which are included in the model description of the digital component.

A digital node can assume the states listed in Table 12.1.

The logic NAND function is realized in sub- circuit ‘MyNand’ with the Boolean function ‘nand(2)’ where A and B are inputs, Y is an output and DPWR, DGND are connections to power and ground, respectively. The timing model ‘D_MyGate’ describes delay times of the NAND gate on the logic level. A special timing model can be assigned to every logical model. The time values signify the minimal, typical, and maximal delay times, respectively, for the rising and falling slope. The given timing model refers to fast 0.5 μm CMOS technology.

The I/O model ‘IO_My’ describes the driving strength at the output (for the 1 state ‘drvh’, for the 0 state ‘drvl’) and the capacitive load represented by an input (‘inld’). In addition, the connection to two AD and DA interfaces is performed, the selection of one of the interfaces is made by a parameter. One of the AD and of the DA interfaces is described in the following paragraph.

The AD interface ‘AtoD_My’ connects the analog node ‘A’ to the automatically inserted node ‘D’ at logical level. The parameter CAPACITANCE is determined by the value of the capacitive load ‘indl’ from the I/O model and applies this load to the analog node. Between the analog node and the power connection a clamping circuit ‘My_Clamp’ is inserted, which is realised by a voltage con- trolled current source ‘G_Clamp’. The core of the AD interface is formed by the digital out- put ‘DOMy’, which the different analog voltage ranges are assigned to an appropriate logical value, e.g., ‘0’ for the range −1.5 V ... + 1.5 V.

The DA interface ‘DtoA_My’ is inserted between a node ‘D’ of a digital output and an analog node ‘A’. The equivalent circuit of an analog output is shown in fig. 12.6.

The actual DA conversion is carried out in the digital input model ‘DINMy’. For each logical value of the digital output the appropriate resistance values are assigned to the resistors Rhigh and Rlow. These form a voltage divider with respect to the power supply voltage, and thus the appropriate analog output voltages according to the logical values are generated, e.g., for logic ‘0’ Rhigh = 100 kΩ and Rlow = 1 Ω , therefore the full power supply voltage is effective at the output (see fig. 12.6).

If the input of the DA interface changes from the old logical value to a new one ‘i’ (with ‘i’ = ‘0’, ‘1’, ‘X’, ‘R’, ‘F’, ‘Z’) the resistors change to their appropriate new values within the time ‘sitsw’. The value of C1 is taken from the parameter ‘indl’ of the I/O model.

The NAND gates previously discussed are chained in a circuit shown in fig. 12.8, embedded in an analog environment. In the lower half the circuit is modeled at transistor level, in the upper half at logic level. Each connection from the logic level to the transistor level is made via an interface. The differences in modeling become clear if the reaction of the different circuit parts to a pulse pattern applied at the input ‘in’ is appreciated.

The technological background for the circuit dis- cussed is 0.5 μm CMOS technology. On the transistor level the transistors are modeled with the SPICE MOS model (LEVEL = 3) [12.1]. At the logic level the models are taken from fig. 12.7, in which the timing model in D_MyGate is adjusted to the SPICE model.

Considering the graph shown in fig. 12.9, the analog stimulus ‘Vin’ is converted into the logical value ‘in’ directly at the input of the first logical gate according to the table given in ‘DOMy’ (fig. 12.7). Because of the relatively long rise and fall times of ‘Vin’ not only ‘0’ and ‘1’ are found but also ‘R’ and ‘F’. The digital node ‘dig2’ follows the stimulus with the delay defined in the model. The value of the resistors at the node ‘dig2’ map the logical value to the corresponding analog voltage ‘Vdig2’ (see fig. 12.6 and ‘DINMy’).

The time functions of the voltages ‘Vdig2’ and ‘Vana2’ correspond to each other quite well especially when considering the delay time at half the maximum voltage value, but not so convincingly with respect to the shape of the rising and falling slope.

The advantage of the digital model is given by the shorter computer time needed for simulation. The circuit with logical models (fig. 12.8 upper part) needs less than 30 % of the computer time compared to the circuit with discrete transistors (fig. 12.8 lower part). If one can do without the analog embedding and works only at logic level, then the computer time needed reduces to 10 %. The savings in computer time will be even more significant, the bigger the circuits are to be modeled at the logic level.