Programmable Logic Devices:Complex Programmable Logic Devices

Complex Programmable Logic Devices

The progressive semiconductor technology allows structures on the chip which are becomming smaller and smaller, even realizing more and more complex logic circuits. Three different basic architectures will be presented in the following. [18.8], [18.10], [18.11], and [18.12] supply detailed information. An up to date outline is given by [18.3]. They are even the main subjects in the special editions [18.4] and/or [18.6].

Multiple Array Matrix (MAX) of ALTERA

ALTERA is the inventor of erasable programmable logic devices (EPLD). With seven types of de- vices they offer solutions for nearly any development requirement today. In the MAX components ALTERA combine several PAL structures to complex programmable logic devices (CPLD). Figure 18.27 shows the architecture in principle of a MAX component.

The functional blocks are called LAB (Logic Ar- ray Block) and consist of the well known macro cells (MC) shown in fig. 18.28 which are supplemented by several Expander Product Terms. A Programmable Interconnect Array (PIA) provides the interconnection amongst the functional blocks. It allows all kinds of connections among all macro cells. The I/O Control Blocks drive the links to the outside.

Such an uncomplicated wiring scheme does not require high standards from the design tools and ensures short predictable signal propagation times. Thus a given clock rate requires only the selection of the appropriate MAX component. There are no losses of velocity to be expected by allocation and wiring.

Each macro cell consists of a D flip flop. Its data input is driven by four programmable AND terms via an OR EXOR structure. The clock input can be switched between a global system clock and an AND term. Two other AND terms influence the storage element directly via the set and/or reset input. The remaining AND term drives the switch- able output driver containing the D input or the Q output of the flip flop.

The vertical input lines of the programmable AND matrix are provided with 4 different sources. In addition to the input pins and the signal feedback of the macro cell they are also driven by the Programmable Interconnect Array and by extension AND terms. The latter allow the extension of the AND terms for programming complex logical expressions.

The ALTERA component, which is at present the most complex one, provides 560 of such macro cells (EPM 9560). A comparable component belonging to the MACH family of VANTIS consists of 512 MCs (M5-512/256). The third component from the ispLSI 80000 family made by LATTICE consists even of 840 MCs (ispLSI8840). This corresponds to a complexity of 45,000 gate equiv-alents. Such a vast application example would exceed the scope of the present chapter and has to be dropped.

It is difficult for the number of pins to keep pace with the increasing number of macro cells. The identification of the MACH component shows that the 512 MCs must share only 256 I/O pins. Every second MC is buried, e.g., it can provide its output value only internally. In practice this does not result in a disadvantage, as the outside often needs some few important signals only.

 

The CPLD chip is often supplied with a different number of pins for different packages. This means that connection signals are abandoned once again. On the other hand, the user can choose amongst different complex CPLDs in one and the same package. If a system modification requires a more powerful component, it matches the foot prints of its predecessor. The printed circuit board remains unchanged, it only gets another assembly.

Logic Cell Arrays (LCA) of XILINX

Probably inspired by the regular structures of the gate arrays, XILINX adopted a chequered design of logic cells for their LCAs as shown in fig. 18.29. The logic cells are connected between each other and between the input/output blocks by means of horizontal and vertical connecting paths. Such an architecture is also called a Field Programmable Gate Array (FPGA).

Each logic cell consists of a configurable logic block (CLB) according to fig. 18.30.

Unlike the macro cell of the CPLD a Look Up Table (LUT) replaces the programmable AND/OR structure in the configurable logic block. This Look Up Table is a mere static random access memory (SRAM) with seven inputs and two out- puts, corresponding to a storage organization of 128 × 2 bits. This allows the programming of two individual combinatorial functions with up to five variables. For sequential tasks the flip flop outputs are also available as the 6th and 7th variable.

Four signals can be selected for the data input of the flip flops. In addition to the two outputs of the Look Up Table and to the flip flop output there is also a direct input ‘data in’ of the logic cell. This output makes the realization of shift registers easier. A clock signal and a reset signal are available separately. The output signals of the logic cell are defined by the Look Up Table or the flip flops.

A configurable logic block corresponds to approximately two macro cells, it has, however, significantly less input signals. For example, if wider AND operations have to be realized, several CLBs have to be cascaded. This is not a problem, as there are sufficient CLBs in most cases. The

two. As complex circuits mostly require a great number of flip flops, ACTEL expand every third logic module with an additional flip flop. At present the most complex ACT component (A54SX64) provides 3,600 combinatorial logic modules and 2,160 storage logic modules. This corresponds to a complexity of 64,000 gate equivalents.

Design steps for highly complex CPLDs or FPGAs

A circuit design with many thousands of gates cannot be realized with Boolean equations only. A possibility of a more complex definition for digital circuits is needed, namely, a hardware definition language such as VHDL. It allows the definition of the future circuit into the design entry according to fig. 18.34.

It is possible to simulate the behavior of the VHDL definition using the EDA support tool. By this means it is possible to detect logical errors and to correct them in the VHDL definition. If the simulation proves the desired behavior, the circuit synthesis will be carried out in the next step. This results in a circuit made of logic gates and flip flops in the form of an Electronic Design Interchange Format (EDIF) netlist and in the form of a VHDL structure description at the same time. The latter is, however, understood by the simulator allows the subsequent simulation which follows the synthesis.

The EDIF netlist may be used by a graphic pro- gram, not shown in fig. 18.34, which is used to draw the wiring diagram. In this case it is the definition for the target technology mapping. The gates and flip flops have to be replaced by the macro cells of the CPLD or by the logic modules of the FPGA. This necessary conversion and optimization of the circuit can be simulated and controlled with respect to the function by the re- vised VHDL structure description. In this phase the EDA tool also monitors the fan out of each gate as the number of the drivable subsequent inputs. Especially in the case of clock signals the driver load often has to be divided into several parallel drivers. It is also possible to try several CPLDs or FPGAs during this design step. Finally, it is a fact that the selected logic circuit is provided with sufficient logic resources.

This is a necessary requirement which is, however, not sufficient for allocating and connecting. All logic elements are now allocated to a physical place on the chip. In the case of a CPLD allocating is not critical, as the connection is always possible because of the great number of inputs into the programmable AND terms. Moreover, the signal delay is defined by connection lines from the beginning. In case of an FPGA there is only a limited number of long, medium, and short connecting lines available in the connecting channels. If these lines are not sufficient the connection remains incomplete. The allocation has to be modified now or even the next larger FPGA has to be taken. There will be varying signal paths with the respective delay times, which will be calculated and provided in the Standard Delay Format (SDF). Together with the VHDL structure description the delay times allow a precise simulation of the timing behaviour. This is the last possibility of control for the developer prior to programming. A second EDIF netlist is set up in parallel containing all topological information, too. It is used by a graphic program to draw a symbolic layout. In a critical situation the allocations and the connections can still be changed here with a layout editor. Afterwards the delay times have to be calculated and simulated once again, of course.

The bit pattern for the programming is realized in the last design step. There are many different ways in which to feed the programming data into the target hardware:

a) EPROM memories, CPLDs in EPROM technique, and non-erasable programmable FPGAs require a programming device;

b)FLASH memories and CPLDs in FLASH technique are In System Programmable (ISP) or In Circuit Reconfigurable (ICR). The JTAG inter- face which belongs to the ‘Boundary Scan Test – BST’ is misused for a short time for this purpose;

c) After each power on of the system, the FPGAs in SRAM technique have to be programmed anew. In ‘slave mode’ they are written like a memory. In ‘master mode’ they read their programming data independently from a non-vola- tile memory device, usually a serial EPROM.

Then they leave their programming status and start to operate.

The correct functioning of the programmed logic device is finally controlled by logic analysis. If errors are detected which had not been revealed in any other preceding simulation, there will be a difficult investigation for the possible reasons. ACTEL offers a unique help with their ‘Silicon Explorer’, which is able to monitor two arbitrary internal nodes via the ‘ActionProbe’ circuit. This allows the back-tracing of a signal path up to the error cause.

The outlined design steps illustrate the need of an extensive EDA software. Such a software is provided by manufacturers of programmable circuit devices (see section 18.6) and by independent software companies (see section 18.6). The recent proposal made by XILINX is called ‘Silicon Xpresso’. It promises to translate a circuit specification received via Internet by means of its ‘WebFITTER’ into the programming data for an XC9500 CPLD. This results in the design method of the 21st century, e.g., the ‘Internet Reconfig- urable Logig’ (IRL).

Comparison and Prospects

Comparing the basic elements of the CPLDs (fig. 18.28) and FPGAs (figures 18.30 and 18.32) their varying sizes are remarkable. A macro cell of the CPLD looks coarse grain compared to the fine grain logic module of the FPGA by ACTEL. The latter can more easily be adapted to the various logic requirements; they can either connect or store. However, if a macro cell is only supposed to connect, the flip flop will remain unused. Typically only approximately 50 % of the available gates of a CPLD are usable gates. With respect to the FP- GAs the limited connection resources only allow an efficiency of 70 to 90 %. Any comparison is therefore open.

Another criterion can be found in the programmable elements. Long lasting programmable fusible links by ACTEL or field effect transistors with isolated gate of the CPLD compete with the volatile programming of SRAM FPGAs. The latter keep their configuration in an always readable non- volatile memory. An unfair product pirate can also read and copy the circuit without hindrance. A copy protection is only guaranteed by durable programmable logic devices; they refuse reading. Advantage CPLD and anti-fuse FPGA.

The SRAM FPGA characteristics to forget what has been programmed becomes a virtue when hardware has to be reconfigured during operation. This requires programming within the sys- tem. For example, an FPGA being an interface to a magnetic disk can be configured for writing and for reading and vice versa. An obvious generalization of such an idea results in a universal programmable hardware made of several SRAM FPGAs. It allows, for example, the emulation of highly complex ASIC designs or the realization of task-specific computers. It is no longer necessary to compile the problem in a computer-specific way, but the computer receives its problem-specific con- figuration.

All advantages of the programmable logic devices lead to their impressive economic success. Ac- cording to table 18.14 the above mentioned sup- pliers cover more than 80 % of the programmable logic devices on the world market. An annual increase of more than 30 % to 7.9 billion dollars is expected for the year 2002. With respect to the ASIC market, however, an annual total increase of only 20 % is estimated [18.7].

There is very strong competition in the component market between the FPGAs and CPLDs. For example, XILINX, who are the market leader in FPGA, are also competing with the (XC9500) as far as CPLDs are concerned. In contrast to this, ALTERA who are the market leader in CPLDs, win market shares with respect to the FPGAs by offering their FLEX components. LATTICE takes over VANTIS.

The above mentioned increases illustrate the attractiveness and great acceptance of programmable logic devices.