Library Design:Maintenance and Porting of Libraries

Maintenance and Porting of Libraries

CMOS processes are still in development to higher resolutions and smaller structure size (see chapter 1). One outcome is a usable process lifetime which is described by design rules lasting only a few years. As the process technology changes they are replaced by new sets of design rules. The designed library of standard cells, which are designed with a certain set of design rules, has to be fitted to each new process and may be partly re-established. So there may be totally new concepts when changing from a process with only two metal layers allowing only channel routing, to a process with more than two metal interconnection layers, allowing area routing without any channels. Simple shrinking of cells without changing details and structures is not sufficient. Further qualitative improvements of processes, as staggering of vias between metal layers, allowing denser routing and cell geometries, have to be taken into account.

Library Design-0044

Maintenance of libraries requires a continuous development of the cells for production yield, which results in small changes of design rules, of which the designer is sometimes not aware. Library maintenance is an important task for the ASIC manufacturer and a key to commercial success.

The transfer of a library to a new process is known as ‘porting’ of the library. This may be needed if a certain successful design should be again manufactured on a new process, without going back to the design level. Porting may also be done to high performance or low power libraries in the same process. In each case a one to one replacement of old cells by an equivalent new cell is required. This has to be differentiated from a redesign at the synthesis level. The development effort for porting a library may be one dimension smaller than a complete re-design if specialized programs (e.g., DREAMQc from SAGANTEC) are used.

Porting needs the following steps:

1. Shrinking and adoption to the new design rules;

2. Quality improvements concerning production yield;

3. Extraction of parasitic capacitances and resis- tances as well as transistor geometries;

4. Simulation of the cell with SPICE at the transis- tor level for all relevant voltages, temperatures and process tolerances;

5. Abstraction of delay times in a predefined way and setting up of description models (VITAL models);

6. Generation of cell abstracts (shapes with exter- nal interface and properties);

7. Qualification of the new cells in the process, capture of cell behaviour by measurements, and adjustment of the models concerning the results.

Figure 17.11 show a library cell ported with DREAMQc . The main arrangement is preserved, but in detail there are many changes. Other programs for library generation and porting are provided by specialized companies like Library Technologies Inc. [17.7], AVANT! Inc., and some other important EDA suppliers. There are further companies, which are designing libraries for a ‘superset’ of CMOS design rules and offer these to ASIC manufacturers. AVANT! offers the library LIBRA PASSPORT [17.2], which is designed with general design rules and shall be a ‘multi- foundry access’ library. From the same source the more rule adopted LIBRA VISA is available. Design porting between manufacturers, both using passport libraries, is very simple and needs only low effort.

Library porting requires detailed knowledge and an extensive effort. A totally different approach is to generate cells automatically from an abstract description using the design rules. This is pos- sible with simple gates and flip flops without to much area overhead (about 10 ... 20 %). In AL- LIANCE, a powerful EDA system developed by Université Pierre et Marie Curie in Paris, the cell library is specified in a metalanguage and must be mapped using the design rules of the technology [17.1]. The method is similar to the ‘stick diagram’ method used in former times for the description of a lay out concept. The area overhead is in the order of 20 %. In many university and prototype runs this is acceptable; however, for industrial designs this may not be enough area effective, but this may change in future. The area wasted by ineffective synthesis may be high today. As device dimensions shrink, the designer has less available core area, and pad limited designs are becoming more and more common.

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