Application Specific Integrated Circuits (ASICs):Design Styles

Design Styles

In this section the different design styles (fig. 16.1) will be presented and discussed with respect to their advantages and disadvantages.

The term semi custom ASICs covers the following different design styles:

• standard cells;

• macro cells;

• gate array;

• PLD;

• FPGA.

Compared with full custom ASICs the design of semi custom ASICs predominantly uses pre- designed cells from libraries.

Often several design styles are used simultaneously when designing an ASIC, e.g., part of the IC can consist of macro cells, the rest of standard cells.

An integrated circuit is manufactured by means of 12 to 25 masks, dependent on the complexity of the technology used. More than half of those are needed to structure transistors and other components. The rest define the connections via metal lines and contacts. The choice of the design style depends on whether all masks for a certain ASIC have to be custom specific or only a part of them. In the latter case wafers can be produced with non- custom specific masks and kept in stock, which saves design and manufacturing time.

Full Custom Design Style

For a full custom ASIC, the design and layout are specific. In the extreme case every component is inserted individually in design and layout. This maximum design freedom enables an optimal de- sign with respect to performance, size and power consumption. The cell layout is possible in what- ever form is required. For a full custom ASIC all masks are specific.

A full custom design shows the advantages of optimal performance, optimal component density, and flexible forms. With a very high number of parts this design style is most economical.

The disadvantages of the full custom design style are:

• high design effort with respect to time and cost;

• high design risk using untested cells.

Design and layout of a full custom ASIC demands a lot of experience. The full custom design style is most common with mixed signal and analog applications.

As an example of a full custom ASIC an IC for direct conversion of digital satellite TV signals will be considered, where the block diagram is shown in fig. 16.3 [16.1]. The incoming signal at RF IN is first amplified and then converted into two orthogonal base band signals by means of two mixers, which are fed with two orthogonal oscillator signals. These signals are generated by an internal delay cell oscillator (DCO), which is synchronized by means of an internal phase detector (PD) with an oscillator connected to an external tank circuit. After external base band filtering the signals are fed back into the IC and amplified in order to reach a sufficiently high level for digitization. The input signals and the oscillator signals of the DCO are in  the frequency range from 950 to 2,150 MHz. The specifications with respect to linearity, to tuning  range of the oscillators, and to deviation from quadrature were so tight that only a full custom design was possible. The design realized by means of a 20 GHz process demanded a very high design effort with several iteration

Figure 16.4 shows the layout of the direct conversion IC. The individual cell outlines typical for full custom design can be recognized. In order to design such a layout a lot of experience is needed because it is so difficult to meet the tight specifications regarding cross talk and quadrature deviation. Even in this pronounced full custom layout repeating cells can be recognized, which is caused partly by symmetry.

The design was accomplished without using pre- designed cells from a library, but, of course, experience gained from previous designs was of great value.

Standard Cells

The term standard cell signifies a pre-defined block, which in general represents a logic function of low complexity (e.g., NAND, NOR or FlipFlop). Figure 16.5 shows a NOR standard cell in ECL technology [16.8] which is used in a standard cell layout (fig. 16.6). The power supply lines are the lines above and below the logic circuit. Input and output are to be found on the left hand and right hand side, respectively.

Standard cells are designed as full custom designs and stored in libraries after having been tested and optimized. The libraries can either be prepared individually or be provided by the manufacturer of the technology, or can be bought from a suit- able company. The placement of standard cells is principally free but normally they are placed in rows of cells with ‘running through’ supply lines. Therefore the cells have to have the same height (see fig. 16.6). Figure 16.6 shows in the upper left part some full custom cells which can be integrated without complying with the standard cell pattern. All masks are specific for a certain ASIC.

The standard cell design is supported by one or several libraries of optimized base cells for which simulation and layout data are available. Some cells can be parameterized. Design and layout in standard cell design are well supported by EDA tools. For details of libraries see chapter 19.

Figure 16.7 shows the top layout of a circuit which consists of standard cells and macro cells dis- cussed in paragraph 16.2.3. Several cell rows can be distinguished. Between the rows wide wiring channels are provided. In order to allow wiring in vertical direction gaps in the cell rows are pro- vided, the so called feed throughs. The standard cell design has some advantages compared with the full custom design:

• the design time is much shorter;

• because of the lower design effort this approach is economical with a medium number of parts;

• the design risk is lower because of the use of a tested library.

Though the standard cell design appears attractive there are still some disadvantages:

• transistors cannot be designed independently and optimally, thus the performance is suboptimal;

• with a small number of parts this approach can be uneconomical as all masks have to be produced.

Macro Cells

The term macro cell or mega cell signifies a pre- defined block, which shows a much higher complexity than a standard cell. Examples of macro cells are:

• RAM cell;

• ROM cell;

• serial interfaces;

• timer;

• arithmetic logic units (ALUs);

• processor cores.

Figure 16.7 shows a macro cell combined with standard cells. The form of a macro cell is flexible. In general no row structure is formed. Macro cells can be placed like standard cells at will. All masks are specific for a certain ASIC.

Macro cells are traded as so called intellectual properties (IP), which are discussed in detail in chapter 7. Hard macro and soft macro have to be distinguished. A hard macro has a fixed layout and is described by a simulation, which includes layout influences. The embedding of a hard macro is equivalent to placing of a component.

A soft macro is typically defined by a netlist or by VHDL code. Layout and simulation data still have to be generated.

The design style with macro cells shows the ad- vantages:

• Fast design with high productivity;

• Short time to market;

• Economical with medium number of parts;

• Low design risk because of use of libraries.

The disadvantages are:

• insertion of a macro cell into an individual de- sign demands a certain effort;

• the price of IPs can be remarkable;

• the design style can be uneconomical with a small number of parts as all masks have to be produced.

Gate Array

On a gate array (GA) transistors; and possibly other components; are connected to form pre- defined base cells which are arranged in a matrix. Each of the squares of the inner section of the ASIC shown in fig. 16.8 represents a base cell. The designer defines only those masks, which signify contacts and connection lines between base cells. This procedure is called personalization of a gate array and this kind is called a masked gate array (MGA). The manufacturer keeps pre- fabricated wafers in stock. Hence only the masks for the metal connections have to be produced for customization which reduces production time and cost.

There are three types of MGAs:

• MGAs with wiring channels;

• Channelless MGAs;

• Structured MGAs.

Figure 16.8 shows a MGA with wiring channels where the base cells of the array are grouped in rows as in a standard cell design. Contrary to the latter the wiring channels cannot be chosen at will but are fixed geometrically. The fixed arrangement of base cells and wiring channels reduces the gate density remarkably compared to a standard cell design.

Figure 16.9 shows a channelless MGA which is also called a Sea of Gates. There are no special wiring channels between the cells. Instead the wiring is arranged across the base cells. This is possible as those base cells which are crossed by wires are not used and have no contact with the wires. Channelless MGAs allow a higher gate density than MGAs with wiring channels because the wiring can be configured freely.

Figure 16.10 shows a so called structured MGA. In addition to matrix-like arranged base cells which cover the main part of the area there are ranges with macro cells which contain a RAM or a processor core for instance. With this approach the possibilities of gate arrays and macro cells can be combined.

The great advantage of gate arrays lies in that only a few masks have to be produced custom specifically. Compared to the previously discussed design styles this leads to shorter design times and to higher economy when only a small number of  parts is required. Compared with standard cell de- sign gate arrays show the disadvantage of a lower equivalent gate density and therefore a higher price per part. In addition analog circuits can only be realized on gate arrays with great difficulty.

In the following paragraph the Gate Forest Technology of IMS will be discussed as an example of the sea of gates technology. This technology provides masters with 2,000 to 120,000 gate equivalents, which can use up to 408 I/0 connections. In addition to digital master cells there are also analog cells. The technology is therefore suitable for mixed signal applications.

The right hand side of fig. 16.11 shows two non- personalized master base cells which contain two NMOS and two PMOS transistors respectively. This shows that a master base cell forms a gate equivalent. The transistor gate wires in polysilicon are already provided yet the cells themselves are unwired.

On the left hand side of fig. 16.11 one cell is wired as an inverter and another cell is wired as a NAND gate with two inputs. In order to personalize the cells two layers ‘metal 1’ and ‘metal 2’ are pro- vided. In addition contacts and vias are needed.

Figure 16.12 shows part of the layout of an A/D- converter described in [16.6] as an example of a personalized gate array. For reasons of clarity only the layers ‘metal 1’ and ‘metal 2’ are shown. Bond pads related to I/O connection and interface circuits can be recognized as also some gates be- longing to the successive approximation register. Normally the gate density is higher than shown

Programmable Logic: FPGA

The term Field Programmable Gate Array (FPGA) signifies programmable logic devices (PLDs) with complex logic cells. As with all PLDs the logic function can be configured custom- specifically by software. Here the FPGAs will be discussed only briefly in order to compare them with other design styles. For a more detailed

discussion see chapter 18.

Figure 16.13 shows that logic cells, interconnect and I/O cells are configurable. Typically the logic cells are arranged as in gate-arrays.

The main advantage of FPGAs lies in the extremely short design time. This is because the configuration can be done by software without technological steps involved. The designer him- self can program the FPGA and sometimes re- program it. This makes FPGAs attractive for a small number of parts or for a prototype design of an ASIC still to be designed. Compared to real ASICs FPGAs have the disadvantages of higher cost per part and usually lower performance.

Comparison of the Design Styles

Table 16.2 shows the different design styles with respect to properties, advantages and disadvantages for comparison. It is difficult in some cases to attribute a certain feature to a certain design style as the actual ASIC project is of influence. Therefore the statements can only be interpreted as typical. The information was partly taken from [16.11], [16.10], [16.13] and [16.3].

Some properties and features require the following brief explanations:

• custom specific masks supplies information on the necessary number of masks and technological steps. In the case of FPGA the actual IC is ready and no masks are needed;

• cell measures signifies the cell form (fixed or variable);

• cell placement signifies the grouping of cells;

• wiring signifies how the cells can be wired;

• area utilization signifies the gate density reached;

• performance is related to speed and power consumption;

• design productivity gives a typical value for the number of gates a designer is able to add to the design per day;

• design time results from the number of the gates needed to produce the ASIC;

• production time refers to the time used for technological steps. In the case of FPGA production is equivalent to a programming procedure;

• economical at number of parts/year provides

a range where a certain design style appears economically sensible. This feature is discussed in detail in the next paragraph.