EDA Tutorial:Synthesis on ASIC Standard Cell Technology

Synthesis on ASIC Standard Cell Technology

Synthesis with the target technology ‘standard cell’ (same is true for gate array) is not very different from synthesis with FPGA technology. The only difference is in the target library, which is built up from basic logic gates with ASICs in contrast to the more complex structured FPGA logic cells. So there are AND, NAND, OR, EXOR, etc. available in each ASIC library, but LUT cells are not. New are complex gates like AND OR INV gates (AOI gates) in different forms, which leads to some improvements in area and power consumption compared with basic gates, saving some interconnection wires in between the sub- gates too. The synthesis tool prefers to use these gates where ever possible. The gate usage statistics of the design mapped to an ASIC library with LEONARDO are shown in table 26.3. Area optimised complex gates are used quite often.

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The synthesized design now contains 225 cells (without GND), about the same as the design made by hand in the beginning table 26.1. The design made by hand was done quasi-optimally, or put in another way: modern synthesis tools allow one to obtain design quality comparable with hand drafted designs, but in a fraction of the design time.

As a comparison, again the core design of the dice counter FSM as a schematics is extracted in fig. 26.11.

The static timing analysis report of LEONARDO is shown in list 26.6. The critical path is now 16.78 nsec, the design is now five times as fast as in FPGA. Synthesis optimisation was on area, not on timing.

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With such timing data for the critical path a timing related post simulation at the gate level using the detailed timing data of the cells used, may be omitted. But this is only allowed for a fully synchronous design with one central clock.

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