Printed Circuit Board Design:Printed Circuit Design Flow and Schematic Entry for PCB Design

Introduction

Performance requirements for electronic devices are constantly growing. The requirements put on printed circuit boards (PCBs) as a basis of these devices are growing in the same way. Without powerful EDA tools being available, the design of modern PCBs with high packing density would no longer be possible. Since each PCB must be optimally fitted to the intended application, many possible variations emerge. Professional EDA tools must therefore offer extreme variability. Manuals with more than 1000 pages are necessary to enable the user to apply these tools. Despite these aids, the tools can actually be used only with a lot of experience and fundamental technical knowledge.

Therefore only some few aspects can be treated in this chapter. The processes which contribute to the understanding of computer aided design tools for PCB design are described. These processes are independent of the particular EDA system. Any- how, it makes sense to describe these processes concretely on the basis of a distinct PCB layout system. The EDA systems of Mentor Graphics and OrCAD were chosen as widely used professional systems.

The features an EDA system should have for PCB design depend on the complexity of the PCBs. The more features a system offers the higher the expenditure is for the training. In this chapter it should be tried to show the most relevant points for the selection of EDA systems for PCB design. The layout process itself and the interrelated problems with layout are described. It will be explained why the careful definition of design rules is important, or why an unfavorable choice of wire spacing may complicate the routing solution. The back annotation is described in detail, too.

Very important for all EDA systems: The provider of the EDA system must be able to supply an exhaustive and up to date library of electronic components that may be placed on the board.

Printed Circuit Design Flow

Figure 25.1 shows the design flow of computer aided PCB design in a block diagram.

According to fig. 25.1 the computer aided design can be subdivided into the design steps:

• schematic entry;

• layout design process;

• post processing.

Schematic Entry for PCB Design

The circuit’s schematics is the basis for the description of an electronic circuit. It is largely independent of the technique of PCB design used. In chapter 3 symbolic schematic capture with graphical symbols is described in detail. Figure 25.2 shows an example of a schematics.

The graphical representation of a schematics shows the functional connections of the circuit clearly. Schematics of large systems are partitioned into several pages and hierarchies. That leads to a significant increase in clearness.

The schematic serves as a basis for all further logical, circuit related, and constructive design steps. The circuitry includes all information necessary for simulation in order to verify the demanded electrical performance. A library contains all models necessary for simulation. From the graphical representation the EDA system generates the equivalent alphanumeric description called the netlist. The netlist file describes the interconnections using the names of nets, components, and pins. Given this netlist the simulator can calculate the circuit’s behaviour. The formats of the netlists (EDIF) used for simulation and further processing are described in section 8.1.

A graphical symbol is assigned to each component. The symbolic, electrical, and geometrical proper- ties of the components are predefined. To each component names have to be assigned, for example, R6 or U7. These names refer to the electric properties as well as the models for simulation, as well as for the geometrical properties for layout.

Powerful EDA systems offer Electrical Rule Check (ERC) tools as an important support for the user.

These tools scan schematic designs and check for conformance to basic design rules and electrical rules. The results of these checks are marked on the schematic pages with ERC markers, and are also listed in a report. Checks performed by

the ERC tools, for example, include unconnected nets, pins, ports, or identical part references. The user can control whether electrical rule violations are reported as errors or as warnings. ERC tools make it easy to locate and fix design errors or electrical errors. Conditions that generate errors can be specified. Critical problems, which have to be fixed, must be defined as errors. Warnings are intended for situations that may or may not be acceptable and may be ignored. All errors have to be fixed before further simulation verifying electrical behaviour.

High performance EDA systems, however, offer not only the possibility of checking simple errors in the circuitry. Furthermore, one can assign limits for tolerable currents and voltages to the component symbols (see section 25.3.1 Libraries). In the ERC run these limits are checked. Thus the reliability of electric circuits can be improved considerably.

It is shown here with the example of the OrCAD system how the designer is able to control the ERC run after its needs. In OrCAD the conditions for whether electrical rules violations are reported as errors or warnings can be selected in the ERC matrix. Figure 25.3 shows a possible decision matrix.

For example, the ERC matrix in fig. 25.3 configures the ERC run to report an error if two outputs are shorted. A warning is reported if an input stays unconnected.

If all required functions are performed and verified by simulation, the netlist used for layout is generated from the schematics in accordance with fig. 25.1. This netlist contains all listed symbols, the device pins and their interconnection, as well as related properties and is used for further layout processing. The netlist may be written in a system- independent file format (EDIF), but is often processed in a company proprietary format and not visible to the user. In the same way, EDIF files with netlists imported from foreign EDA systems may be further processed. In many cases it is possible to write or edit the netlist directly in alphanumerical form with a text editor, too.

Libraries

Huge and actual libraries are an important pre- requirement for the effective use of an EDA sys- tem. The libraries contain components with all their properties and their electrical and geometrical data. Properties are, e.g., the model parameters for circuit simulation as well as geometrical data for layout, see, for example, fig. 25.1. A component from the library must be completely defined by the properties for the dedicated EDA tool. If a circuit shall be analysed with a simulator the electrical models must be completely available.

In general, the symbols used for components are based on standard definitions. Sometimes internal company conventions are used. The symbols are maintained in the symbol library. Symbols which are not available in the attached library must be generated by the user. The generation of new symbols with all required properties may be very costly. Therefore it must kept in mind that a

large symbol library must be available with the acquisition of an EDA system. The quality and the capability of an EDA system for PCB design depends decisively on the quality of the component library provided.

The so-called Board Process Library of Men- tor Graphics contains more than 14,000 digital, analog, passive, electro-mechanical, and optoelectronic components. All digital (and most of the other) components in the library contain data sheet information, electrical models for simulation, thermal model for thermal simulation, and other ERC properties.

If no symbol exists for a specific component in the symbol library it must be created by the user. With the creation of a symbol object a relationship must be established between the component symbolic representation, its electrical properties, and its geo- metrical footprint. When the object is stored there must be consistency between geometry, symbolic representation, allocation of pins, the sequence of pins, and further properties. The required data for creation of a symbol object for a given component depend on the software used and the component properties.

The Mentor Graphics EDA system uses the following data:

Fig. 25.3 Decision matrix for ERC configuration;

W stand for Warning, E stands for Error

• Graphical symbolic representation;

• Characterization of component type (e.g., IC, transistor, resistor, diode);

• Geometry of the footprint (dimensions, number of pins, layout of pins, power supply connections);

• Allocation between the symbol representation and the physical footprint;

• Information about functional equivalent circuits and swappable pins in a physical package (e.g., in a series 7400 package are four logically equivalent NAND gates, both inputs of a NAND gate show same behaviour and by this they are swappable);

• Geometry of the pin pad (width of wire connection, size and form of the necessary pads);

• Data for automatic assembly support and manufacturing tolerances;

• Cross-references to libraries, which support simulation and test (e.g., model names);

• Limits for components loads (e.g., maximal thermal dissipation power).

Graphical Symbols

Graphical symbols characterize the electrical properties of components in a graphical representation. The geometrical properties are described by the package. The symbol object contains all the in-

formation which is required for PCB design. This includes the part number, the type of component, number of pins, pin assignment, etc. As simple examples fig. 25.4 shows the graphical symbol of a npntransitor and of a resistor.

An EDA software must offer tools for creating user specific symbols as well as to modify existing symbol objects and to add and modify related symbol properties. This tool is usually called the symbol editor.

For layout creation special properties must be as- signed to the symbol objects. With graphical symbols taken from a library, the properties are already defined, only the values must be edited. In addition to standard properties, company specific properties may be added (e.g., part number code, provider code, etc.).

As an example for properties used in PCB design see table 25.1.

Component Geometries

The component geometry defines the physical

shape and characteristics of a component. In Mentor Graphics systems these chracteristics are named ‘component attributes’. This includes, e.g., the pin numbers, pin location, or the component placement outline. Further component geometry

characteristics are component height, restrictions on placement orientation, assignment of a component specific padstack, the reference name, and an addition of drill holes if they are needed for manufacturing.

Professional EDA systems offer tools which use the thermal outline definition along with component height information to develop a model for thermal analysis. The Mentor Graphics pro- grams Auto Therm and Auto Therm MCM accept such models. The component geometry allows multiple thermal outlines. There may be one ther- mal outline defined that applies when the component is placed on the top of the board and a dif- ferent thermal outline may be defined that applies when the component is placed on the bottom of the board.

Figure 25.5 shows two examples of component packages.

The layout process flow needs a referral (mapping) of the physical pins on the component to the logical pins of the symbols. This mapping has to be unique.

There are different possibilities to map the pins:

1. One-to-one pin assignment (fig. 25.6);

2. Assignment by a mapping file (fig. 25.7).

For an explanation of these two different concepts an operational amplifier in a ‘dual in line’ package with 14 pins is selected. Figure 25.6 shows the first form of assignment. For each pin on the symbol a physical pin on the package is assigned. The phys- ical pin numbers on the component are identical with the logic pin numbers of the symbols.

The second form of assignment is shown in fig. 25.7, by the creation of a mapping file which maps the physical pins of the package to the logic pins of the symbols. Any logical pin name may be chosen. For instance, in fig. 25.7 the logical pins are named ‘IN-, IN+, V-, OUT, V+’. These logical pins names are associated with the physical pin numbers ‘4, 5, 6, 10, 11’.

The one-to-one assignment (fig. 25.6) has the ad- vantage that the effort of creating a new symbol is low. The disadvantage however is that the assignment must be modified if the package is changed (fig. 25.8).

The disadvantage of a mapping file (fig. 25.7) is that the expenses for creating mapping files are higher than for one-to-one assignments. On the other hand, it is an advantage that a mapping file is independent of the package. The change of a component is possible without additional expenditure, too. Figure 25.8 shows an example: The DIL package with 14 pins (fig. 25.7) is replaced by a TO5 package with 12 pins.

The main advantage of the mapping file method- ology results from fig. 25.8: if a large library of components is available, the user can change the package type during the layout process without changing the schematic itself, e.g. the pin numbers are preserved. With a new package the layout can be routed again, whereas the schematic remains unchanged.