EDA Tutorial:Synthesis and Emulation on FPGA

Synthesis and Emulation on FPGA

The limitations of verification by functional digital simulation are quite obvious if the sound generation is involved. One cannot deduce from the traces 1), what a melody tone ‘sounds’ like if the tone’s pitch is comfortable and the sound’s duration long enough. Also the ergonomics of button operation, the time constants used, and the run off times may be badly evaluated from traces on a screen. From this it is very important to synthesize this circuit on FPGA and emulate it there. As a prototype, all functions may be operated in real time several times and the reactions may be observed in many repetitions, something which is impossible in digital simulation because of the long run times.

For educational purposes FPGA emulations have high value, because each student is able to verify his own design by reprogramming the FPGA. The result is easy to inspect for the instructor. In the practice of the courses we have the experience that even if all designs passes digital simulation, every second design shows up errors or specification deviations in the FPGA emulation. Everybody may deduce his own consequences from this experience for the verification performance of larger, more complex designs.

EDA Tutorial-0173

EDA Tutorial-0174

Synthesis was carried out with LEONARDO (Men- tor Graphics); fig. 26.9 shows a screen display of the compile window.

Synthesis generates the netlists (EDIF) for the tar- get technology, which may be re-transformed to schematics. Figure 26.10 shows a section with the dice counter FSM, and how it is generated by synthesis of the VHDL code. There are again three flip flops used, but with more complex post decoding. This may result from a certain code for the counter having been pre-defined (binary, gray code, etc.) during the set up of the synthesis.

Some sections from the netlist generated by the synthesis program are shown in list 26.4.

The netlist contains several calls of a LUT function 1) which reflects the internal structure of the ALTERA FLEX 10K FPGA architecture used. The schematics are not directly readable in this form. The re-transformed schematics is again generated from these LUT functions. To allow a comparison it is mapped onto generic gates as AND, OR and EXOR cells as well as D flip flops. Table 26.2 shows design statistics for the target technology ALTERA FLEX 10K.

EDA Tutorial-0175EDA Tutorial-0176

It is interesting that the design now needs only 158 elements, 45 of which are d flip flops. The number does not tell us very much, of more interest is the statement that 117 logic cells, which are the primary resources of the FPGA, are used. The smallest FPGA from the FLEX 10K series, the 10K10 with 576 logic elements 1), will be sufficient for this design. A synthesis on other FPGA families (as there are MAX 7000 or even the older version MAX 5000) may also be successful.

After synthesis a timing analysis is reported, see list 26.5, showing a ‘critical path’ of 80 nsec. The dice may be clocked at up to 10 MHz, so 32 kHz will work without any problem.

Synthesis and consequent emulation of the design on FPGA improves the trust in the design and is inevitable for circuits with ergonomic interfaces and long timing chains. Misinterpretation of specification and inconsistencies may be detected and eliminated early, the validated VHDL code may then be taken as a ‘golden code’ for different target technologies, which now have to be checked only for timing behaviour.

Comments

Post a Comment

Popular posts from this blog

EDA Tutorial:Place and Route in a Standard Cell Design Style

Image
Place and Route in a Standard Cell Design Style In the design of FPGA circuits, after the synthesis of the EDIF files, the compiling and programming of the FPGA device, everything is defined and the component is completely configured. With ASIC designs, there are two possible scenarios: • Delivery of the design to an ASIC provider in the form of a so called simulate d netlist (EDIF); • Place and Route of the design with one’s own tools, verification of the results, and delivering of the design as a geometrically exact GD S II File . For similar designs in industry the netlist version is frequently chosen, but here the second scenario which includes the bac k en d processing , the phys- ical design, will be demonstrated in more detail. This needs special software tools, which allow the mask design at the lowest geometry level, and tools for checking the generated geometries against the predefined design rules ( Desig n Rule Che c k , DRC ), and allow one to extract parasitics and el...
Read more

Overview of EDA Tools and Design Concepts:Architecture, Methodology, and Design Flow.

Image
Architecture, Methodology, and Design Flow Nora: What do designers mean when they speak of chip "architectures"? IC Architectures Andrea: That is more jargon. There are many ways to implement an IC design. The designer chooses a specific physical IC architecture to implement the design (e.g., GA, SC, FPGA, or custom). Do you know about those? Nora: A little—someone at Sandbox said they were different ways to make an IC. He emphasized the time-to-market issue. Andrea: That's right. Here, let me sketch you a picture of some IC architectures. (See Figure 4.3 .) Note the four different physical IC architectures. The block-based IC is usually a custom chip. The individual blocks may be custom logic, or memory blocks or microprocessors. The cells in the standard cell and FPGA chips may be many different kinds of gates. And FPGAs come in various flavors and styles as well. The gate array is a fixed array, usually of the same complex gate. The gate array and FPGA chip...
Read more

Design using Standard Description Languages:The simulation model in VHDL

Image
The simulation model in VHDL After a look at concurrent signal statements in chapter 4.3, basic mechanisms of the language can be discussed in detail. Originally the language VHDL was developed for simulation only. A dis- cussion about the theory of operation of a VHDL simulator helps to understand VHDL modelling and simplifies the choice of suitable language constructs to describe hardware constructs. The topic simulation model has an emphasis on: • Driving signals; • Delta delay mechanisms; • Modelling of delay times. Drivers Every concurrent statement, including processes, causes an event responsible for the progress of a signal. Within the simulator there is a list containing points in time to schedule signal events. Such an entry in that list is called a transaction. This list is the basic information for scheduling signal values during simulation (fig. 4.22). A change of a signal value caused by an entry in that list, is called an event in that signal. If a new entry is the ...
Read more