EDA Tutorial:Completion of the design with Pad Cells and Validation of the Entire Design

Completion of the design with Pad Cells and Validation of the Entire Design

The circuits developed lack any pad cells for the input and output signals of the chip. Selection of these cells is subject to considerations of the external circuit. This is output loading for driver cells, and for input cells the behaviour of the input signal determines which kind of cell has to be used.

In the dice circuit, a Schmitt Trigger Input cell is used for the input signal derived from the button to obtain a hysteresis behaviour for slowly increasing signals. Bouncing of the button has to be suppressed by the FSM which processes the button signal and which synchronizes the signal with the internal clock. This functionality has to be respected during the design of the control FSM and is

EDA Tutorial-0179

not part of the pad cell selection considerations. To be brief, there are no pad cells with anti bouncing characteristics.

For all other input cells standard input pad cells are selected, most of them with an internal Pull Up 1) resistor. The internal pull up resistors presents a logical ‘1’ to the pad even when there is no connection to the cell at all; in the same way a pull down resistor generates a ‘0’ input. If the pin is connected to a circuit such internal pull up or pull down resistors may be a source of power consumption, and so the later usage scenario has to be considered carefully.

On the output driver side the load on the circuit from external components has to be considered, such as the capacity of the wires on the printed circuit board or of connected cables. In our case these are the LEDs, consuming about 3 mA, so a simple standard output pad cell will do what is required. In many libraries there are pad cells with driver capabilities up to 24 mA; if more load capability is needed pad cells may be used in parallel.

When positioning the pad cells on the peripheral ring the power supply method has to be considered carefully. So there should be no power driver cells in the direct neighbourhood of sensitive analog or oscillator cells. If this happens, an influence on the phase, or even a severe disturbance of the frequency, of the oscillator may take place.

The power supply of an ASIC is provided in two distinct ways for core and pad ring. The sup- ply systems are connected with each other on the printed circuit board, not on the chip. This avoids mutual interference caused by the series resistance and impedance of the bonding connections. But not only the ohmic resistance is of importance, also a low inductance has to be realized for a good power supply. Usually the power supply pad cells are arranged in the middle of the sides of the chip or in the corners, Vdd and Vss are placed on opposite sides, Vdd_core beside the Vdd_pad and Vss_core beside the Vss_pad.

The relative placement of the pad cells is pre- defined by placement properties at the schematics level or as attributes in the structured VHDL file. Figure 26.12 shows the schematic of the dice project with predefined pad cells.

The delay of the pad cells is usually much greater than the delay of core cells. The complete design with connected pad cells and external circuitry and loads has to be validated in a final and detailed gate simulation. The result of this simulation may then be directly compared to test (measured) results later.

For an industrial design the latest test structures have to be introduced, so far such structures have not been included previously during synthesis. In a design of this kind normally a scan path and JTAG connections are added, both of which may be done automatically. The test patterns needed may be generated with ATPG tools automatically. In this case this was omitted because a functional test is sufficient for these low production numbers and an automatic wafer test is not intended.

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