Programmable Logic Devices:The Basic Concept of a Programmable Logic Device

Programmable logic devices (PLDs) belong to the integrated circuits (IC). They divide up into immediately available standard ICs and ‘application specific’ integrated circuits (ASIC), which are yet to be made in a rather time consuming way. From the manufacturer’s point of view PLDs are standard products for a maximum clientele, from the customer’s point of view, however, they are application specific after programming. Thus the PLDs combine the advantage of immediate availability with application specific functionality which ex- plains their attractiveness.

The Basic Concept of a Programmable Logic Device

How can an already complete circuit still be changed? The forerunners show the close relation- ship to the programmable memory which reveals the secret.

Historical Milestones

In the middle of the 1960s, Harris Semiconductor developed the first PLD, namely, a fuse configurable diode matrix. The diodes connected horizontal lines with vertical lines. These connections could be interrupted by a high current phase during programming.

In 1970 the first programmable read-only memory (PROM) developed from it. Such a memory is presented in the following section.

In 1975 Intersil and Signetics presented the first FPLAs (Field Programmable Logic Array) at nearly the same time. FPLAs are an obvious generalization of the memory structure. They had, however, no commercial success owing to the lack of computer support for programming.

It was only the simplification to PAL (Programmable Array Logic) by Monolithic Memories Inc. (MMI) in 1978 which succeeded on the market. Thanks to good customer support by a PAL manual and the computer support by the PAL assembler (PALASM), which is a program for the translation of Boolean equations into the program data, the demand rapidly exceeded the production capacity. After the takeover of MMI by Advanced Micro Devices (AMD), its daughter Vantis Corp. still offers 5 families of PALs today. This unbroken popularity justifies the detailed study of these components in the sections 18.2 to 18.4 according to the documents [18.1], [18.2] and [18.9].

The development to increasingly more complex programmable logic devices (CPLD), respectively, Field Programmable Gate Array (FPGA) is dealt with in section 18.5.

From The Memory To The Programmable Logic Device

A memory assigns the associated data to the al- located address. This can also be used for the implementation of logic. Figure 18.1 shows the logic AND operation for the input signals e1 and e0 which result in the output signal a. The truth table in 18.1 shows the values of ‘a’ for all possible input combinations of e1 and e0. This table can also be taken as an assignment of a 4 × 1 bit memory. Thus the programmable memory is a programmable logic device at the same time.

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Figure 18.2 shows the general realization of a 4 × 2 bit PROM. The two address inputs are fed into a diode matrix as true and inverted inputs. The vertical lines at the pull up resistors realize positive wired ANDs. A ‘low’ (0) at an effective diode is sufficient to set the AND line to ‘low’. In order to a ‘high’ (1) at the AND line, all diodes have to be stimulated with ‘high’. Only one of the 4 AND lines can have the value ‘high’. This line selects the memory word to be addressed. This is the reason why this circuit part is called the address decoder. It is simply an AND matrix.

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The second part of the circuit diagram in figure 18.2 is a transistor matrix. The horizontal lines with the pull down resistors can be pulled up to ‘high’ by any of the 4 connected transistors. They realize a positive OR operation (a wired OR). Each transistor is connected to the OR line by a fusible link. If this fusible link is blown during programming, the isolated transistor does not operate and the line remains at ‘low’. Each AND line of the address decoder selects a pair of transistors  showing a 2 bit wide data word at the memory output. This part of the circuit is the data memory and a simple OR matrix.

The fixed AND matrix followed by the programmable OR matrix is shown in a slightly simplified way in figure 18.3a). An ‘×’ shown at the crossing of vertical and horizontal lines represents a diode and/or an effective transistor. Several logic AND operations grouped by an OR  operation constitute the Sum Of Products (SOP). There will be an ideal hardware for the realization of logical expressions when the AND matrix is fully covered, too, as shown in figure 18.3b). It is sufficient to have one diode at all the crossings which can also be made ineffective by a fusible link. This development of the memory was called FPLA (Field Programmable Logic Array). Both AND and OR matrixes are programmable.

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The third version in figure 18.3c) does without the programmability of the OR matrix and merely combines 2 AND lines each with one OR line. This decreases the universality; however, it still meets most of the practical requirements and makes programming much easier. This reversal of the memory, namely a programmable AND matrix followed by a fixed OR matrix, is called PAL (Programmable Array Logic). These PALs started the invasion of programmable logic devices.

Realization Possibilities of Programmable Elements

Apart from the idea of a programmable AND-OR structure, the programmable memory also brought about the production technology and the realization of the programmable elements. In the PROM a thin wire, being a fusible link, connects every single transistor with the OR line. This fusible link can be destroyed by a current pulse. This interruption is irreversible. Components with fusible links can only be programmed once (One Time Programmable – OTP). A development style of trial and error is impossible with respect to these components.

The desire to have a possibility of correction led to the EPLD (Erasable Programmable Logic Device). The fusible link is replaced by an N  channel field effect transistor with isolated gate as shown in fig. 18.4.

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In the case of a positive gate potential the FET conducts similarly to an unblown fusible link. The isolated gate is separated from the source diffusion by means of a very thin oxide layer only. When the programming voltage at the control gate is high and positive, negative charge carriers from the source diffusion will penetrate this weak point and will charge the isolated gate with a negative voltage. The field effect transistor will now block similarly to a blown fusible link. The isolated gate will be discharged again by an external energy supply by means of ultraviolet light, making the field effect transistor conductive again. Thus programming can be erased within 20 minutes.

An advanced version can be erased electrically (electrically erasable programmable logic de- vice – EEPLD) which takes place within milliseconds. Without erase measures the charge is guaranteed to remain in the isolated gate for 10 years, which means that this kind of programming is long lasting.

Another possibility of electrically operating switches is the static random access memory – SRAM. The bi-stable circuit made of two over- cross connected inverters stores the information for opening or blocking a field effect transistor as shown in fig. 18.5. This information is lost when the voltage is disconnected, thus the programming is volatile. Therefore programming has to be carried out first after each switching on of the voltage. In addition, reprogramming is possible even during operation. Such a component finds its programming data in an external non-volatile memory.

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The latest kind of programming memory cells re-verses the principle of fusible links (therefore anti-fuse). Instead of interrupting a connection the separating insulation at the crossing of two lines is stripped off, thus creating a connection. Figure 18.6 shows two versions of such programming memory cells which hardly need any additional space. The destruction of a special insulating layer can, of course, be made only once (OTP), it is, however, durable instead.

The planned application of a programmed logic device may have an influence on the choice of the programming type. In the case of an unsafe voltage supply with frequent voltage drops, an SRAM-PLD will not work because of the constant reprogramming process. If there are still changes of wiring logic to be expected, an OTP-PLD is not to be considered.

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