Digital Simulation:SDF Format for Standardized Digital Models

SDF Format for Standardized Digital Models

There are various activities for creating libraries which are not specific to a manufacturer. The goal of the initiative is to standardize and increase the quality of models for cell libraries concerning ASICS, independent of IC manufacturers.The objectives of the VITAL (VHDL Initiative Towards ASIC Libraries) initiative can be summed up in one sentence:

Accelerate the development of sign off quality ASIC macrocell simulation libraries written in VHDL by leveraging existing methodologies of model development.

In 1992 there existed only a few ASIC cell libraries. The main problem was to specify the timing parameters in a standard way. VHDL was the language for source code chosen by VITAL. The VITAL ASIC Modeling Specification [11.8] was created. It allows the modelling of timing behavior of logic circuits in VHDL in a standardized and effective way. Thus standardized circuit models can be used in simulators of different vendors. They may be parameterized for diverse technologies of different vendors. VITAL uses constructs of VERILOG Language which is already an industry standard.

Details of VITAL files will be explained in chapter 19. Properties of models are interchanged in Standard Delay Format (SDF), which allows the timing behavior of logic circuits to be described.

The behavior of integrated circuits is determined by its logic and the varying parameters of production. However, the specifications of semiconductor manufacturers are considered to be conservative. In most cases this leads to the function verified via simulation being the function of the real hardware, provided that the parameters are used correctly.

The organization Open Verilog International (OVI) published its first Standard SDF in 1993. A newer version will become IEEE Standard 1497.

The definition of the SDF format is determined by the software tools used by the designer. Thus the information interchange between different development platforms becomes possible. The SDF format uses ASCII code which is widely generally accepted.

The SDF file is created by the Timing Calculator (fig. 11.2), which is part of the software tool used.

The SDF file contains only timing data. The timing behavior of the single logic elements is not described in the SDF file. It is in the library with cell timing models. In the simulator logic modules are analyzed and the specific delay times are calculated accordingly. Minimal, typical, and maximum delays are taken into account as well as the differences between rising and falling edges, provided that these parameters are specified in the timing models.

The Timing Calculator creates the SDF file. The Timing Calculator accesses models for simulation of the timing for interconnections. The parameters used for the timing model are evaluated. The result is on one hand the pin to pin delay and on the other hand the distributed delay times of every single path. The delay times may be calculated in the pre-layout phase or in the post-layout phase of the design. Either expected layout parameters or parameters of the actual layout (Back Annotation) can be used.

If there is a design change the SDF file must be generated again because it is directly based on data of the design.

The Annotator is the program which has to match data in the SDF file with the design. It may be part of the simulator or part of the development tool. Each region in the design identified in the SDF file must be located and its timing model be found. The values of the SDF file will be inserted into the models.

In addition to the timing information from back annotation forward annotation is also supported by SDF. Using forward annotation the design engineer may specify timing constraints, e.g., for the data path. The timing constraints will be observed in the development tools used later in the design process (fig. 11.3). Floor planning, layout, or routing may use this information. The result will be a circuit meeting its specification or a circuit with parts which are malfunctioning.

Specific behavior of logic elements, such as masking of a short pulse at the input which does not propagate to the output (Output Pulse Propagation) may be specified in a SDF file. In this case a limit can be specified, up to which a short impulse

Digital Simulation-0154Digital Simulation-0155

Modeling Timing Checks, such as setup, hold, and recovery timing checks are supported by SDF. The SDF file is therefore an important interface for circuit design. It will gradually gain importance if standardization of SDF continues

Comments

Post a Comment

Popular posts from this blog

Design using Standard Description Languages:The simulation model in VHDL

Image
The simulation model in VHDL After a look at concurrent signal statements in chapter 4.3, basic mechanisms of the language can be discussed in detail. Originally the language VHDL was developed for simulation only. A dis- cussion about the theory of operation of a VHDL simulator helps to understand VHDL modelling and simplifies the choice of suitable language constructs to describe hardware constructs. The topic simulation model has an emphasis on: • Driving signals; • Delta delay mechanisms; • Modelling of delay times. Drivers Every concurrent statement, including processes, causes an event responsible for the progress of a signal. Within the simulator there is a list containing points in time to schedule signal events. Such an entry in that list is called a transaction. This list is the basic information for scheduling signal values during simulation (fig. 4.22). A change of a signal value caused by an entry in that list, is called an event in that signal. If a new entry is the ...
Read more

EDA Tutorial:Place and Route in a Standard Cell Design Style

Image
Place and Route in a Standard Cell Design Style In the design of FPGA circuits, after the synthesis of the EDIF files, the compiling and programming of the FPGA device, everything is defined and the component is completely configured. With ASIC designs, there are two possible scenarios: • Delivery of the design to an ASIC provider in the form of a so called simulate d netlist (EDIF); • Place and Route of the design with one’s own tools, verification of the results, and delivering of the design as a geometrically exact GD S II File . For similar designs in industry the netlist version is frequently chosen, but here the second scenario which includes the bac k en d processing , the phys- ical design, will be demonstrated in more detail. This needs special software tools, which allow the mask design at the lowest geometry level, and tools for checking the generated geometries against the predefined design rules ( Desig n Rule Che c k , DRC ), and allow one to extract parasitics and el...
Read more

Overview of EDA Tools and Design Concepts:Major Classes of EDA Tools.

Image
Introduction In the next few chapters, we will discuss specific kinds of EDA tools. In this chapter, we provide an overview of the EDA tool world. There are several EDA-related concepts which are helpful to understand the EDA tools and the design process. These include: Design Views Hierarchy Design Chip Architecture Methodology Design Flow Tool Suites Nora of Sandbox, Inc., is meeting again with Andrea, an ASIC engineer who works for Fabless Design, Inc. Nora has asked to learn more about the use of EDA tools. Let us listen in on their discussion. Nora: Hello again, Andrea. Did you like the party the other evening? Andrea: Yes, very much. Sandbox has both outstanding tools and great parties. Nora: We seem to be continually developing new tools. I am a little unclear why that is. Tool Improvements Andrea: That's because each generation of semiconductor process improvements shrinks the size of the transistors and wires. The number of transistors and wires...
Read more