Library Design:Pad Cell Libraries.

Pad Cell Libraries

Pad cells, the connection to the surrounding world, are collected in special pad cell libraries. They are very important. Pad cells perform the following tasks for a chip:

• Driving of external loads up to 24 mA;

• Buffering of input signals;

• Connection to supply voltage for core and pad area;

• Shielding of all chip internal structures against electro static discharge (ESD), transients and wrong poling;

• Adaptation of logic levels to external circuitry.

Table 17.10 gives a view of a typical pad cell library. Some manufacturers provide pad cells with different pitch for pad limited designs or for core limited designs. Cells for pad limited design are long and narrow, so they may be placed on a grid as small as 100 μm. Pad cells for core limited design are short but wide and need a pitch larger than 100 μm, but have a smaller shape of the peripheral ring.

In the library there are input and output cells for CMOS and for TTL signal levels at the output ports. There are simple driver cells with normal load capability and cells with increased driver capability (more fan out) and cells with tristate outputs and bi-directional input/outputs. Available input cells are standard input cells with input driver

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Schmitt trigger cells shall be used with signals with low slew rates. There are further cells with integrated pull up and pull down resistors with selectable resistance. Output cells may be single ended, so there are open drain n-channel outputs as well as open drain p-channel outputs. For analogue designs there are pad cells without any buffers or input drivers, only with protection structures against ESD. See fig. 17.6 for lay out examples.

Output pad cells are classified for driving capability, sometimes measured in mA, and for slew rate, the signal slope steepness. A signal with high slew rate and strong driving capability may emit large levels of electromagnetic radiation and give a rise to interference and coupling to other signals on a printed circuit board. With rise times below 1 nsec, there are emissions in the GHz range, which will be emitted by each wire connected to the pad acting as an antenna. So it makes sense to limit or lower the slew rate of the signal to avoid noisy emissions. Cells with defined slew rate, specially designed for this purpose, contain a miller capacitance in the driver, which generates a trapezoidal signal transition from one logic level to the other. This cell should be used when only slow output signals are needed, e.g., to switch a LED display. Cells with programmable slew rate are available today in all FPGA families.

Pad cells are used for the power supply of the core V DDcore and V SScore as well as for the peripheral ring of the pad cells themselves V DDpad and VSSpad. Both power rails are not connected directly on the chip but on the board in order to improve the decoupling of the power supply systems. The corners of the periphery area are build from special corner cells which may have additional pad and guard structures and close the external power ring. For analogue cells, there are additional power pads, defining a complete separate analogue power supply domain, which will not be coupled to the digital supply. With chips today having several hundreds of I/O pads, more than one pair of supply pads are placed on each side of the chip.

All pad cells are provided with protecting guard structures (see fig. 17.7) which consist of integrated diodes to the pad supply rings. Input pads contain an additional input series resistance which forms an effective filter together with the input capacitance, against electrostatic discharge pulses

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(ESD). The lay out is made in such a way that the requirements of a test with the human body model fig. 17.8 are met. This model contains a capacity of 100 pF charged up to 2000 V, and discharged via a resistance of 1500 Ohms to the pad.

Library Design-0037

For many technical applications the ESD protection after fig. 17.8 is not sufficient; for example in the automobile as well as in the military sec- tor significant higher levels are requested. Many manufacturers design their pad cells to a test voltage of 4 ... 5 kV, which is about four times better than the human body’s model.

Output cells should be protected against short circuit, this can be done by series resistances, or better, by limiting the current of the driver.

Beside these standard I/O cells there may be special cells for clock oscillators, allowing a direct connection of a quartz crystal to the chip.

The design of one’s own pad cells in a full custom style is very risky because of the ESD problems and the required guard and protection structures. It should be avoided and library cells preferred wherever possible.

Pad cells are described by models in the same way as core cells and are characterised by their timing behaviour. During simulation the external loads (the capacitances of the pins) as well as the board structures may be taken into account. Compared to the core cells, the delay times are remarkably large, the power consumption too. Partitioning of functions over several chips which are connected by a printed circuit board is ineffective for delay and power consumption, in contrast to an entire solution on a single chip.

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