Design for Testability:Sequential Circuits

Sequential Circuits

Since sequential circuits can store data there are many internal states that are often hard to control and to observe from outside. For that reason

testing sequential circuits is, in general, a difficult task. As an example figure 15.33 sketches a circuit which is partitioned into a 16 bit counter and a purely combinatorial sub-circuit. The only input of the counter is an enable signal that is used to increment the counter at the rising edge of a clock signal.

To test the overflow output α of the counter for stuck at faults one needs in each case 216 clock periods to invert signal α . In the worst case the input patterns needed to enable the increment operation may even depend on the state of the counter. Then one needs a sequence of 216 non-trivial test patterns to control signal α and obviously the sketched circuit is hard to test.

In practice one has to avoid circuits which are so hard to test and there are two different approaches to how this can be done. On the one hand, circuit extensions can be used to improve controllability and observability of signals. For example, this can be done using the Scan Path method described in section 15.5.1. This method is often part of design tools for improving testability in a way such that test pattern generators for combinatorial circuits (section 15.4) can also be used for sequential circuits.

An alternative approach is to directly design circuits in such a way that they become easy to test. Such design techniques are called design for testability and are presented in section 15.6.

Scan Path

To simplify the test problem many ASIC design systems only allow the designer to use special flip flops as sequential elements and they forbid other kinds of feedbacks. If other sequential elements are needed, for instance such as RAM blocks, they must be separable in such a way that distinct tests can be applied to circuit and storage blocks. Thus we only have to consider sequential circuits of the type sketched in figure 15.34.

Separating such a circuit at flip flops (broken lines in the sketch) we obtain several combinatorial sub- circuits Si. Therefore the circuit can be represented by a purely combinatorial part and a storage block consisting of flip flops as shown in figure 15.35.

The essential idea of the Scan Path technique is to introduce a test mode in order to separate the storage block consisting of k flip flops from the combinatorial part of the circuit. Then the remain- ing combinatorial sub-circuit has n + k primary inputs (x1, ... , xn, z1, ..., zk) and m + k primary outputs (y1, ... , ym, zt , ... , zt ). Of course in practice one cannot insert additional pads for each flip flop. Therefore for test mode all flip flops are connected to build a shift register which is also called a Scan Path. With only one additional input pad ‘scan_in’ all flip flops can be sequentially loaded with data and simultaneously the former data can be sequentially observed at the output pad ‘scan_out’. Thus using the Scan Path all flip flops are easy to control and easy to observe.

However, for this implementation we have to assume that all flip flops are using the same clock signal which can be externally controlled and which is also available during test mode. Thus when using this type of Scan Path it is not allowed to derive clock signals from data signals. Other requirements for the circuit will be considered in more detail in section 15.5.2.

Using a Scan Path it is very simple to apply an automatic test pattern generation. At first one ignores all flip flops and applies the automatic test pattern generation for combinatorial circuits (section 15.4) considering n+k primary inputs and m+k primary outputs. Then n signals of a derived test pattern are directly applied to the circuit and the other k input signals have to be sequentially written into the Scan Path during test mode. Afterwards for one clock period test_mode is set to 0 to enable normal operation of the circuit and to transfer the test_mode = 1. Simultaneously with sequentially reading, the next test pattern can be written to the shift register. In this way, to apply l test patterns one needs a total of l · (k + 1) + k clock cycles. At the same time the Scan Path is also tested.

A disadvantage of that test method is the slow operation rate of the circuit during test because k preparing clock cycles are necessary to apply one test pattern. In this way timing problems within the circuit may not be detected because critical signals are applied much earlier than in normal operation. This effect can be avoided by using Master/Slave

flip flops, so that data from the Scan Path is applied to the circuit only after test mode is terminated.

Another reason for using more complex flip flops for a Scan Path is to introduce a separate clock signal for test mode. In this way one avoids the restriction that all flip flops of the sequential circuit have to be triggered by the same clock signal. In figure 15.37 a Master/Slave flip flop with two clock signals is shown.

With Level Sensitive Scan Design (LSSD) introduced by IBM even three clock pulses are used, one for the normal operation of the circuit, one for the master, and one for the slave of the flip flop.

Automatic synthesis of a Scan Path by a design system also has to define the arrangement of flip flops within the Scan Path. This information is also needed in order to correctly apply test patterns to the combinatorial part of the circuit. In principle an arbitrary arrangement of flip flops can be used. But then automatic placement and routing of layout synthesis may become more difficult. Therefore synthesis of a Scan Path should at least consider the rough placement of flip flops within a floor plan to create a Scan Path with short interconnections (figure 15.38). That method of considering geometrical information of a preliminary layout for logic synthesis is not unusual. For example, synthesis of clock trees is often done also using a floor plan.

Frequently used modifications of the Scan Path technique are to include only a subset of flip flops (partial Scan Path) or to distribute flip flops to several Scan Paths. This way using additional hardware (additional pads or multiplexing to existing pads) sub-circuits can be tested separately and the total time for testing can be reduced.

Requirements for a Scan Path

To improve the testability of a circuit by an automatic insertion of a Scan Path the circuit has to satisfy some special requirements. Since the circuit state will be controlled by the Scan Path the circuit should only contain such sequential components as can be included in a shift register. For example, it is not allowed to use latches that are set asynchronously.

Of course all edge triggered flip flops within a Scan Path have to be sensitive to the same kind of edge (rising or falling) and if the same clock signal is used in normal mode and test mode then all flip flops have to be triggered by the same external clock signal.

If, as an exception, there are different clock signals clk1 and clk2 in a circuit, as shown in part a) of figure 15.39, one has to add a multiplexer and an external selection signal clk_select to create a unique clock signal to be used for the Scan Path during test mode. This modification is shown in part b) of figure 15.39.

To automatically generate test patterns for such a circuit the generator needs some additional information about how to activate the Scan Path. In particular, for the example one has to specify that clk_select = 1 is necessary for using the Scan Path.

Something similar applies when using asynchronous reset inputs of flip flops. Such reset signals also have to be controlled by primary inputs and should be inactive during test.

Also flip flops with an enable input need special attention. Since the enable signal should not disturb Scan Path operations the enable input of flip flops has to be replaced by an additional multiplexer at the data input, as shown in figure 15.40.

Since RAM blocks also can not be included into a Scan Path they have to be un-coupled during test mode so that they can be tested separately. Thus, all data, address, and control lines of the memory have to be made controllable and observable. For example, registers built from flip flops are a suitable interface between circuit and memory, because they can be included in the Scan Path. In this way during test mode the circuit will read data from the Scan Path instead of reading from memory. Accordingly, output data will not be written into RAM but will be written to the Scan Path.

Testing Sequential Circuits without Scan Path

The Scan Path presented in section 15.5.1 enlarges chip area and delay times and results in longer test sequences. Therefore one also tries to include only those flip flops in the Scan Path that are actually hard to control or hard to observe. For example, it is demonstrated in [15.24] that often the fault coverage obtained for a complete Scan Path can also be achieved by a suitably chosen relatively short partial Scan Path.

As an alternative to a Scan Path one can try to achieve a good controllability and observability using only available data lines. However, this means a substantially larger execution time for test pattern generation because the generation problem no longer can be reduced to the special case of combinatorial circuits. Exemplarily, the difficulties occurring will be demonstrated for flip flops used in data registers and finite state machines.

Logic synthesis of high level synthesis tools has to allocate data of an algorithm to hardware registers. For this allocation task there are several optimization criteria such as chip area needed, attainable clock rate, number of clock cycles needed for a computation and rate of data flow. A further criterion of synthesis is the testability of the generated circuit. For this criterion synthesis tools have to estimate the controllability and observability of internal data (section 15.4.6). Then with data path synthesis data has to be distributed on available registers, in such a way that easy and hard to control (resp., to observe) variables share the same registers. In this way all registers become controllable and observable well without additional hardware [15.10]. Only if such an allocation can- not be found must additional control signals be introduced to improve testability [15.15].

For finite state machines there are further difficulties. While using a Scan Path it is easy to set all state machines of a circuit to well defined states, but without a Scan Path it becomes harder to reach the initial state of an automaton from any current state. To test for a fault the test pattern generator not only has to determine suitable states for stimulating and propagating the fault, but it also has to create sequences of input patterns to reach those states.

When several automata are serially connected within a circuit the problem arises of how to derive an input sequence to create some output sequence needed for the test. To simplify such problems one should introduce to all automata reset states which are easy to attain, thus improving the testability of the circuit [15.36].

A further difficulty arises for finite state machines if the specification only defines attainable states of normal operations. For example, in figure 15.41 a Mealy automaton with three states is given. For a binary coding of states one needs two flip flops, and thus the obtained circuit actually has four states. If in any way (because of random events at ‘power on’) the circuit does indeed reach the fourth state then its behavior is not defined.

The state transmission function and the output function are both implemented by combinatorial circuits. To observe a stuck at fault within the combinatorial part of the automaton it then may become necessary to enter an illegal state. Since illegal states do not occur during normal operation such a fault is not relevant for the correct operation of the automaton. Therefore it is called a sequentially redundant fault [15.12]. But unfortunately such irrelevant faults may lead to an extremely large execution time for pattern generation using only a gate level circuit description. This is because it is very hard to determine the nonobservability of faults, resp., the un-reachability of states.

Similarly to a logic minimization eliminating redundant signals of combinatorial circuits that cause non-detectable faults, a synthesis tool should also perform a circuit optimization to eliminate sequentially redundant faults.

As an example we consider the automaton specified by table 15.16 which has three states, an input x, and an output y. As a special feature we assume that in practice input x = 1 does not occur for state (10). Therefore the appropriate entry is missing in the specification. For logic synthesis this obviously means an additional degree of freedom.

Figure 15.42 shows an implementation of the state transmission function and of the output function.

For this combinatorial circuit fault ‘α s-a-1’ can only be detected using the test patterns (x, s0, s1) = (1, 1, 0) or (x, s0, s1) = (1, 0, 0). But according to the specification in table 15.16 for both inputs there is no admissible state transition such that the fault can not be observed if the automaton is part of a more complex sequential circuit. Such a fault, which can only be detected by illegal state transmissions, is called a functionally redundant fault.

In figure 15.43 a modified implementation of the automaton is given. It also satisfies the specification of table 15.16, but does not contain function- ally redundant faults. For this implementation the specification was completed in such a way that for the state (10) and the illegal input x = 1 the next state becomes (11) and the output is y = 1. Then the automaton corresponds to the state diagram shown in figure 15.41. The example demonstrates that this kind of logic synthesis has large influence upon the execution time of test pattern generation. In particular, it is shown that a favorable imple- mentation for test pattern generation may even need fewer gates.

In [15.27] the effect of logic synthesis on the performance of test pattern generation is investigated for the example of re-timing operations. In order to shorten critical paths and to achieve faster clock rates combinatorial parts of a circuit are equally distributed between flip flops. This operation of logic synthesis is called re-timing. In particular, re-timing can insert additional flip flops. For example, the logical behavior of both circuits presented in figure 15.44 is identical, but signal paths are differently partitioned amongst clock periods.

Although re-timing does not modify the logical behavior of a circuit and thus has no effect on testability of stuck at faults, it turns out that of- ten the performance of test pattern generation is drastically reduced by re-timing. This is because for every additional flip flop the size of the search space for test patterns doubles and the percentage of relevant states becomes smaller.

To solve this problem one can use adaptive ATPG tools that use heuristics to avoid irrelevant states (resp., eliminate irrelevant flip flops).