Design for Testability:Importance of Chip Testing.

This section gives an overview of various aspects of testing chips. It considers the modeling of errors, automatic test pattern generation, and how to design circuits that can easily been tested. Usually in ASIC design systems there are special tools for supporting the testing of chips. Examples are the programs Quick-Fault and Fast-Scan from Mentor Graphics, Verifault from Cadence and Test Compiler from Synopsys. Additionally, synthesis tools typically support Scan Path and Boundary Scan techniques (sections 15.5 and 15.7). Section 15.6 gives some more specialized test structures which may be implemented by the chip designer, or are already part of parameterized cell generators.

Importance of Chip Testing

In spite of all efforts to increase the quality of chip manufacturing, production faults can not be avoided, and therefore also defect chips will be produced. For example, pollution can cause shorts between wires or interruptions of individual lines. The probability of such defects drastically grows  with the size of a chip. In figure 15.1 the damaged chips on a wafer are marked by a cross.

Let pdefect be the probability of a square unit of chip area being damaged by pollution. Then the prob- ability for a correctly produced chip with area N  becomes p = (1 − pdefect)N assuming that failures  occur independently for all square units.

With increasing complexity of fabricated circuits the chip test gains ever more significance, since the rejection rate rises drastically (figure 15.2). Of course one has to detect faulty chips as soon as possible. Therefore a first production test is performed on the wafer in order to avoid packaging costs for defective chips.

Since each individual fabricated chip must be tested, testing is very time consuming and thus expensive. Therefore one tries to reduce the total number of test patterns per chip as far as possible. Furthermore, testing complex VLSI chips is difficult because the behavior of an extremely large number of devices (> 1 million) has to be tested using only a few pads (< 100).

Design for Testability-0275_thumb

Design for Testability-0276_thumb

Black Box Test

The aim of testing is to check whether a chip is in accordance with its specification. A black box test checks the chip behavior without using knowledge about the structure of the implemented circuit. This will be demonstrated by a simple example.

A full adder can be specified by its function table given in table 15.1. The black box test of a full adder circuit will use all 23 = 8 possible input patterns to check whether the chip really derives correct output signals carry and sum for all inputs

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For combinatorial circuits the number of test pat- terns needed for a black box test grows exponentially with the number of primary inputs. For large circuits this is a much too high expenditure. Thus, for instance, testing an adder with a data width of 16 bits already needs 232 = 4 294 967 296 test patterns. Therefore the question arises of how to test the circuit with fewer test patterns. Un- fortunately, without knowledge about the circuit implementation this is not possible. For example the combinatorial circuit could be implemented in terms of a ROM containing the data of the function table. The primary inputs then correspond to  address lines of the ROM and the primary outputs are the data lines.

In this way the implementation of a full adder only needs a ROM with 8 words of length 2 bits. Using the input word (a, b, c) as a 3 bit address the ROM will output the data word (carry, sum) in accordance with table 15.1. Since an error could be situated in each individual ROM cell, one cannot proceed with fewer test patterns. In order to reduce the number of test patterns one needs additional assumptions about the possible types of faults. For this purpose we consider fault models.

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