Overview of EDA Tools and Design Concepts:Major Classes of EDA Tools.

Introduction

In the next few chapters, we will discuss specific kinds of EDA tools. In this chapter, we provide an overview of the EDA tool world.

There are several EDA-related concepts which are helpful to understand the EDA tools and the design process. These include:

• Design Views

• Hierarchy

• Design

• Chip Architecture

• Methodology

• Design Flow

• Tool Suites

Nora of Sandbox, Inc., is meeting again with Andrea, an ASIC engineer who works for Fabless Design, Inc. Nora has asked to learn more about the use of EDA tools. Let us listen in on their discussion.

Nora:

Hello again, Andrea. Did you like the party the other evening?

Andrea:

Yes, very much. Sandbox has both outstanding tools and great parties.

Nora:

We seem to be continually developing new tools. I am a little unclear why that is.

Tool Improvements

Andrea:

That's because each generation of semiconductor process improvements shrinks the size of the transistors and wires. The number of transistors and wires on the chip increases dramatically.

The wires and transistors are smaller and closer together. This increases the electrical coupling between transistors and wires, which can cause more failures. The chips run at higher frequencies, which leads to interference on the wires. Power increases with faster chips and that can cause thermal problems as well.

All of these issues cause new kinds of design obstacles. New EDA tools are created to address these design challenges. Tools also need more capability just to handle the increased numbers of transistors and wires.

That is why developers are constantly updating and creating new EDA tools.

Major Classes of EDA Tools

Nora:

There are so many EDA tools. Is there a grouping or order to them?

Andrea:

Yes. There are three major groups or classes of EDA tools. They follow a general design sequence. Let me show you this overall sequence. (See Figure 4.1.)

Note the three main groups: electronic system level (ESL) design, IC front-end (FE), and IC back-end (BE) design. Each consists of design tasks, followed by verification or checking steps. If the checking steps find errors, the design is revised. The designers repeat (iterate) this design-verify loop as needed. The iteration may even go back to the front-end or system design requirements if back-end errors are found.

Electronic System-Level Design Tools

Andrea:

ESL design uses one class of tools. Just as the house architect describes the customers' requirements, so does the electronic product engineer.

The architect builds a model (on paper or on the computer) to see how the design will look. The system engineer also makes a high-level computer model to see if the design will work.

The architect may try several models, exploring different materials or house layouts. The system engineer does design exploration, trying different design approaches (such as implementing functions in hardware or software).

Nora:

So there are EDA tools to help with defining requirements, modeling the system, and exploring different design approaches?

Andrea:

Yes. Most of an electronic system can now fit on a chip. Therefore, IC designers and system designers now need to know about both system design and IC design!

Traditionally, IC design falls into two major divisions. These are the front-end design and the back-end design.

Nora:

So we have system, front-end and back-end tools. At the party, I think I talked with engineers who used each kind. What are the front-end tools?

Front-end Design Tools

Andrea:

Front-end IC design tools include design capture, verification, and synthesis tools. A house architect records design ideas on paper or on a computer. IC designers similarly capture their design ideas on a computer, using words or graphical symbols (design capture).

The next task is to verify or test that the design ideas look right or work correctly. For this, architects and engineers used to build detailed miniature models (prototypes) of their designs.

However, now computer programs can simulate almost anything. Simulation is faster and less expensive than prototypes. Architects can present a simulated walk-through of the house. (You can even see this in real estate ads on the Internet!) IC designers can simulate every operation of the IC, from input to output.

IC design verification includes simulation tools to verify that the design behaves and performs as intended. Additional analysis and checking tools ensure that the design meets all the design rules. (Design rules are like the electrical and plumbing codes which cities require for safe buildings.)

The third major front-end task is synthesis. An architect transforms the house design into a list of specific parts, materials, and building instructions. IC synthesis transforms the design description into a specific set of components and wire connections. A synthesis program selects the transistors, gates, or cells from a library.

The synthesis output is a netlist file of transistors, gates, or cells and connecting wires (nets). This is the dividing line between the front-end and back-end design steps.

Nora:

Okay, front-end tools help with design capture, verification, and synthesis. What are back-end tools?

Back-end Design Tools

Andrea:

The back-end design tools are collectively known as physical design tools. They aid with the general layout of the chip (floorplanning). They also help the detailed placement (locations) of the transistors, cells, or IP blocks on the chip.

After placement, routing tools (routers) help plan the physical routing of the interconnect paths.

Timing-check tools calculate delays with the new information extracted from the actual physical layout.

Other tools check the many electrical and physical design rules. Most physical design rules relate to manufacturing tolerances. ("The space between wires may not be less than 2 microns" is an example of a physical design rule.)

The output of the back-end design flow is a tapeout file. It contains the graphical patterns (polygons) for each transistor and wire on the IC.

Nora:

So we have floorplanning, placement, routing, extraction, and rule-checking tools in the back-end physical design?

Andrea:

Yes. Let me show you a table of typical tool types and who uses them, in each area. (See Table 4.1.)

Andrea:

The table summarizes what we have been talking about. You see the three main areas, the primary tool users, and the major tool types. The two divisions (FE and BE) overlap now as more physical design and estimation is done up-front. (We haven't talked about all these tools yet.)

Other tools not in the three main areas address documentation, change, and version control. Chip packaging also has its own suite of design tools. So do analog, radio frequency (RF) and mixed-signal design tools. (SeeAppendix C for more information on these.)

Note that front-end design can be done at two levels. Tools work either at the detailed gate level, or at the higher register transfer level (RTL).

Table 4.1. Major EDA Tools

ELECTRONIC SYSTEM-LEVEL (ESL) DESIGN

Users

Tools

Architect

ESL Design Entry

System Engineer

ESL Verification

IC System Engineer

ESL Modeling

ESL Timing Analysis

FRONT-END (FE) DESIGN

REGISTER LEVEL

Users

Tools

RTL Entry

System Engineer

Test Bench

Logic Designer

RTL Simulation

ASIC Designer

Formal Verification

Test Engineer

Design for Test

Timing Design

Thermal Design

Power Design

Signal Integrity Design

Synthesis to Gates

GATE LEVEL

Users

Tools

Logic Designer

Schematic Capture

ASIC Designer

Gate Level Simulation

BACK-END (BE) DESIGN

Users

Tools

Floorplanning

Layout—Place & Route

Layout Designer

Electrical Rules Check

Logic Designer

Physical Rules Check

ASIC Designer

Extractors & Delay Calculators

Test Engineer

Timing Analysis

Power Analysis

Thermal Analysis

Other Analyses