Design using Standard Description Languages:The simulation model in VHDL

The simulation model in VHDL

After a look at concurrent signal statements in chapter 4.3, basic mechanisms of the language can be discussed in detail. Originally the language VHDL was developed for simulation only. A dis- cussion about the theory of operation of a VHDL simulator helps to understand VHDL modelling and simplifies the choice of suitable language constructs to describe hardware constructs. The topic simulation model has an emphasis on:

• Driving signals;

• Delta delay mechanisms;

• Modelling of delay times.

Drivers

Every concurrent statement, including processes, causes an event responsible for the progress of a signal. Within the simulator there is a list containing points in time to schedule signal events. Such an entry in that list is called a transaction. This list is the basic information for scheduling signal values during simulation (fig. 4.22). A change of a signal value caused by an entry in that list, is called an event in that signal. If a new entry is the same as the actual signal value this signal assignment has no effect.

Delta Delay Mechanism

To answer the question of how the simulator finds an unequivocal result despite several concurrent signal assignments, it is helpful to look at a sim- ulation cycle in detail. A simulation cycle with a step forward in time (e.g., 1 ns) and a cycle without progress in time (Δt = 0 ns) will be distinguished.

VHDL simulators are driven by events. The simu- lator advances the simulation time and searches all driver lists to find out if an event, that is a change of state of a signal, is due to take place. Signals associated with a driving list containing an entry for the time being, will be updated actual time to the corresponding value of the driver list. The new signal value is presented by the graphical output of the simulator now. All other signals without a scheduled transaction keep the values they have.

A change of state of a signal now activates the simulator. The simulator examines all concurrent statements to find out if any of these statements have an effect on that signal. If this is the case, those statements would be executed as well. After all concurrent statements have been examined, new values and new entries to the driving list can be a consequence. If a signal assignment has a zero delay time, all concurrent statements associated with the modified signal must be reviewed again. There must be no increase in time, zero delay cycles will apply.

A stable simulation result is achieved when there are no new entries in the driver list at this point in time. This means all signals remain stable for at least one delta time. After that the simulation time step can increase again. In this case the step in time does not have a constant increment, it can be dynamically enlarged according to the next event.

This sequence of events maps parallel activities within a VHDL description to sequential steps of a simulator program. The sequence of concurrent statements in a VHDL text makes no difference to the results of the simulation . Events in signals only determine the work flow. This property makes VHDL simulation very efficient, because computer time will be only needed when there is a change of state in the simulation model.

There is an amazing situation in figure 4.24. De- spite both inputs lset and reset carrying a static low logic level, the outputs x_del and y_del change state periodically. The circuit oscillates. The period of the oscillation corresponds exactly to the delay of the two signal assignments, x_del and y_del. If the delay is decreased the change of state of the signals increase. The extreme case, a delay of zero seconds, causes infinite delta steps. The simulator does not find a stable result and eventually exits. Table 4.3 shows the simulation run.

Modelling of Delay Times

A VHDL description (RTL) to be synthesized usually does not contain delay times in signal assignments. Delay times caused by delays at the gate level (e.g., combinatorial logic) or by propagation delays (flip flops) depend on the target technology, which will be defined at a later point in time of the design cycle. However, the specification of delay can describe the timing behavior after synthesis or provide a tool for generating complex input stimuli in a simulation environment.

There are two different types of delays:

• A transport delay for modelling delays on wires;

• Inertial delay, causing suppression of very short pulses.

Transport Delay

The effect of a transport delay: the new value is added to the list of the events at the scheduled point in time. If there are other entries in the list, scheduling events at a later point in time, these entries will be cancelled now (fig. 4.25).

The main difference from a transport delay is that the history of the signal plays a part as well. Delayed signals are built according to the following rules:

• Label the new entry to the driving list;

• Label that entry prior to the new entry which has

• Label the entry which is responsible for the present signal value;

• Remove all entries with no labels.

Explanations regarding the sequence in figure 4.26:

1. Point in time: t = 10 ns: Entry of ’1’ at t = 25 ns.

2. Point in time: t = 15 ns:

Entry of ’0’ at t = 30 ns. Labelling of entries at 0 ns and 30 ns, entry at 25 ns deleted.

3. Point in time: t = 20 ns:

Entry of ’1’ at t = 35 ns, entry at 30 ns deleted.

4. Point in time: t = 40 ns:

Entry of ’1’ at t = 35 ns already active. No entries between t = 40 ns and t = 55 ns. No entries to be deleted.

The following question must be answered: What is the minimum pulse width of the signal sel in figure 4.27 which will produce a visible signal change on output y? Is there a difference of simulation results using inertial or transport delays?