Design for Testability:IDDQ Test

IDDQ Test

With the IDDQ test method one determines the power consumption of a chip at a stable state (quiescent current). Then a chip is called faulty if there is a significant increase of current for some test pattern. Such an increase of current might be owed to a physical defect of the chip. Nevertheless, it is conceivable that despite the defect the functional behavior of the chip is correct. Thus the method of IDDQ testing is rather a defect oriented method than an error oriented method. It may also be used to improve the reliability of chips (section 15.10). Within the model of IDDQ faults all conceivable faults are considered which may increase power consumption. For example, the fault model includes bridging faults, gate ox- ide shorts, transistor stuck on faults, and some stuck at faults.

Functional Undetectable Defects

With functional tests one tries to stimulate a fault and to propagate resulting erroneous signals to a primary output. But for an IDDQ test one uses the fact that, when stimulated, many faults cause an increased power consumption, such that it is not necessary to propagate the fault, but only to measure the flow of current for the chip.

This method will be demonstrated for the example of a CMOS inverter shown in figure 15.61. In any stable state exactly one of the two transistors is conducting and therefore the output y is either connected to VDD or to VSS. Apart from parasitic effects there is only a flow of current within the transient state of switching signals.

In the case of a stuck on fault at the transistor T1 for the input x = 1 both transistors are conducting and there is an increased quiescent current between VDD and VSS. Depending on the resistance of transistor channels, the value of the output signal y results from the voltage divider built by T1 and T2.

It is also possible that despite the fault the voltage at the output y may be interpreted as the correct logic value. Thus the logical behavior of the circuit may be correct. However, because of the effect of electron migration the fault may later cause fail- ures after a longer period of operation. Therefore on using the IDDQ test it is possible to detect defects that can not yet be detected by functional tests.

An increased current can even be caused by a transistor stuck open fault. This is shown by the circuit example given in figure 15.62. Here the p- transistor T1 and the n-transistor T2 form a trans- mission gate, transmitting the input value x to the internal node y for of c = 1. Here the n-transistor is well suited to transmit the value 0 and the p- transistor is well suited to transmit 1. With the fault ‘T1 stuck open’ and the input x = 1 there is a bad transmission of ‘1’, only generating a ‘weak 1’ at node y because the voltage at y is reduced by the threshold voltage of transistor T2. As a consequence it may happen that the transistor T3 of the succeeding inverter is not perfectly locked, and therefore there is an erroneous current between VDD and VSS.

In a similar way also interruptions of wires may cause an increased power consumption because of undefined signal levels. Often such faults are also detected by functional tests as stuck at faults. Further faults that cause an increase of quiescent current are bridging faults, and gate oxide shorts.

IDDQ Test Patterns

An important advantage of the IDDQ test is that generating test patterns is much simpler than for functional tests. This shall be demonstrated for the example of a hard combinatorial bridging fault (section 15.4.1) at two wires α and β . To detect the fault by an IDDQ test it is sufficient to drive both signals α and β by different values. This will cause a high current because of the short circuit. Thus the characteristic equation for test patterns simply becomes α ⊕ β = 1 and is correct for all kinds of bridging faults.

For an automatic IDDQ test pattern generation with common test pattern generators it is very easy to model the bridging fault. One only has to extend the circuit by an XOR gate performing α ⊕ β and to introduce the output of the XOR gate as an madditional primary output to be tested for ‘stuck at-0’. Each pattern producing the signal 1 at the new output can be used as a test pattern.

Since for computing IDDQ test patterns fault propagation can be omitted, there are more possible test patterns for a fault than for functional tests. Thus an IDDQ test needs fewer test patterns. Unfortunately, in practice a sufficiently precise current measurement is relatively time consuming, and therefore to limit test effort one has to keep the number of IDDQ measurements as small as possible. Thus for a given number of measurements one determines a set of test patterns obtaining a maximal fault coverage.

Since the model of stuck at faults does not deter- mine a unique kind of physical defect, some stuck at faults might increase quiescent current, whilest others do not. If, for example, an ‘α s-a-0’ fault is owed to a short between wire α and the supply line VSS then stimulating the fault by α = 1 will, of course, produce high current. But this may not be true for an interruption of a wire. Thus the IDDQ method cannot replace functional tests but can extend such tests to improve defect coverage. One should never use IDDQ measurements to reduce the number of functional test patterns.

As an extreme example we consider the red/black coloring method presented in section 15.4.6. If all stuck at faults could be detected by IDDQ measurements then the circuits obtained would be completely testable for stuck at faults with only two test patterns.

Multiple faults do not cause additional problems for IDDQ testing. For example it can be shown that when simple design rules are respected [15.21] every test pattern detecting a single bridging fault F will also detect any multiple bridging fault with F is involved.

IDDQ test pattern generation also has to calculate the intensity of quiescent current. For this one may use an extended switch level simulation also considering realistic resistances of transistors. With a given accuracy of measurement such a simulation can be used to determine whether the erroneous current is sufficiently high to be recognized. On the other hand, such simulations can also be used to determine the accuracy needed for an IDDQ measurement.

In order to receive meaningful results IDDQ tests should be restricted to such test patterns producing a low power consumption for correct chips. Section 15.8.5 considers in more detail which properties have to be satisfied so that a circuit is well suited for IDDQ tests.

IDDQ Threshold Value

One problem with IDDQ measurements is that of deciding for which amount of quiescent current a chip should be classified as faulty. Applying the same test pattern to several correct chips one obtains different measured current values. Figure 15.63 shows the typically obtained standard distribution (Gauss curve) for current measurement.

The average value of that distribution denotes the typical quiescent current of a correct chip. But be- cause of deviations during manufacture actual values will differ from the expected value. Repeating the measurement for several chips all containing  the same IDDQ fault, the curve of the distribution would be shifted to the right by the amount of the erroneous current.

The threshold value for an IDDQ measurement should be determined according to the expected erroneous current. In figure 15.63 this is the value I0. The area below the distribution curve to the right of I0 then corresponds to the probability that a correct chip is classified as defective. This probability can be used to define the threshold value I0. Then one has to compare the costs of both kinds of erroneous decisions: What are the expected costs if a defect chip remains undetected and what does is cost to classify a correct chip as faulty?

Principle of IDDQ Measurement

In figure 15.64 several techniques are shown to measure a quiescent current [15.37]. When inserting a resistor into the power supply of a chip the voltage drop at the resistor is a measure for the flow of current. But since such a resistor within a supply line will reduce the applied voltage it has to be shorted by a transistor for normal operation of the chip.

As an alternative approach the resistor can be re- placed by a capacitor. Again, for normal operation it is shorted and unloaded. For testing, the transistor is opened and the capacitor is loaded by the quiescent current. Then, after a fixed period of waiting, the voltage at the capacitor is a measure for the quiescent current. If it extends a certain threshold value the chip fails the IDDQ test.

It is common to all approaches that IDDQ measurement with sufficient accuracy is relatively time consuming. Thus in practice one has to restrict the number of measurements to a small subset of IDDQ test patterns, thereby obtaining a significant improvement of defect coverage.

In [15.23] a measurement technique is proposed using the fast pin electronics of functional test equipment to observe the power supply also. This way it is possible to perform an IDDQ test without hardware overhead. As shown in figure 15.65, one uses several driver channels of the tester for the power supply of the chip. One of them is configured to become a monitor channel. For IDDQ measurement the VSS drivers are turned into the high impedance state. Then after a fixed time of waiting the increase of voltage observed at the pin VSS (figure 15.66) is again a measure for the quiescent current.

As an alternative to external IDDQ tests the current can also be measured on the chip using special sensors (BICS: Built In Current Sensor) [15.28], [15.47]. Since the current measurement should not obtain too much influence over the performance of normal operation, the circuit is partitioned into several sub-circuits which can be observed separately. With this technique self-tests are also possible.

IDDQ Testability

In order to apply an IDDQ test the circuit has to satisfy special properties. For example, as mentioned above, the correct circuit should have a very low quiescent current such that the erroneous current is easily detectable.

Therefore the circuit may not use oscillators, and whenever there are dynamic storage blocks they have to be separated for the test. Also pull up resistors have to be disabled for the test mode, and for pad drivers, analog cells, and bipolar sub- circuits a separate power supply is needed because they typically have a high power consumption.

Buses always should carry well defined signals. Otherwise additional drivers have to be provided to force buses to default values whenever there is no actual write operation. Thereby, of course, conflicting write operations must be avoided.

Because of the necessary time for exact current measurement the circuit must be able to work at a slow clock rate. Therefore if the chip itself is monitoring the system clock this must be deactivated for the test.

Furthermore, for regular structured circuits such as storage blocks, IDDQ tests are not of interest be- cause there are already specialized tests available with high defect coverage.

Further Parameter Tests

Since one reason for an increased quiescent current is that of illegal signal levels, the observation of voltage levels at critical signals is also an alternative to IDDQ tests. For example, a simple sensor  for voltage levels consisting of only three inverters is presented in [15.43]. Figure 15.68 shows that this BIVS (Built in Intermediate Voltage Sensor) only produces an output of ‘1’ if the input signal can not clearly be interpreted as logic 0 or logic 1.

In section 15.8 it has been discussed which defects may increase the quiescent current of a circuit. Of course faults can also cause an increased current during the phase transient states. To discover such effects one uses IDDT tests, observing transient current.

For example, in [15.42] an on chip sensor is presented to measure current peaks during switching operations. In particular, it is suitable for chips with low power supply.

A combination of IDDQ and IDDT tests consists of measuring the total energy needed by a chip to perform a set of test patterns. For this task a method is described in [15.39] such that the chip under test obtains its power from a capacitor which is reloaded whenever its voltage drops under a critical limit. Then the number of test patterns which can be executed between two reload operations defines an energy signature which can be used to decide whether the chip is correct. Advantages of this method are a fast test procedure and a simple measurement process, because IDDQ and IDDT currents are accumulated.