Library Design:Libraries for Printed Circuit Design (IBIS).

Libraries for Printed Circuit Design (IBIS)

For the large domain of printed circuit design, which can only touched upon here, libraries are of central importance. There are four basic libraries:

• symbol libraries;

• model libraries;

• packages libraries;

• pad libraries;

to mention the most important. Symbol libraries are discussed in chapter 3 in detail, there are the IEC libraries and the older, but still widely used, ANSI libraries. Each electrical block has a symbol, and the ports or pins are numerated in a definite way. The geometry of the block is found in the package library, here are standards like JEDEC with different housings (DIL, SO, TSOP, ...) common. Symbol and form are referenced through a mapping in such a way that each symbol port belongs to a geometric pin of the housing. The form of the pin, the geometric footprint on the board (pad), may be again varied, so there may be housings which require holes in the board, other may be soldered to the surface (SMD devices).

Model libraries are offered by nearly all vendors, sometimes as SPICE model description. Simulation of the board functions may then be done with programs like PSPICE or ELDO, also in a mixed digital/analogue style. Simulation of complex circuits is possible by these methods, but the results are often not satisfactory, the effort high, and not good enough in critical points. One reason for that is that there are effects coming from the spatial distribution of components on the printed circuit board. Signals show reflections and cou- plings, which are not included in the netlist and are not simulated. With thousands of connections, programs like SPICE are not well suited, even if all parasitic effects were modelled.

To verify complex, high frequency printed circuit boards with regards to their interconnection behaviour and signal integrity, a different approach is required. It has to be focussed on the signal

integrity of the widely geometric distributed board structure, not on the general function of the board. The development of modern motherboards with operating frequencies above 100 MHz would not have been impossible without these new tools.

A detailed description of the input/output structures of the connected components in a standardized EDA format is important for simulation of the interconnect and signal integrity. The IBIS standard ANSI/EIA-656 [17.3] sets up the foundation for all further developments. IBIS stands for I/O Buffer Information Specification. The actual version 3.2 allows one to describe the electrical behaviour of input and output structures of integrated circuits, secondary boards, connectors, etc. in a machine readable format. IBIS models are available from many electronic manufacturers [17.4]. The standard is distributed, maintained, and further developed by EIA IBIS Open Forum, an association with more than 35 manufacturers. IBIS models are administered in libraries and can be read and processed by specialized programs.

IBIS models describe only the input/output structures, not the functions of the circuits. The functionality of the circuit is not released by the provider and, unfortunately, may be very complex. Classical applications are bus models (e.g., for simulation of PCI bus or processor boards with high clock frequencies). IBIS development and standardization was mostly initiated and driven by INTEL. More information can be found in [17.4].

A company association in Japan is actually developing a similar standard ‘IMIC’ for analogue integrated circuits: ‘Standard for electronic behavioural specification of integrated circuit analogue characteristics’.

Comments

Post a Comment

Popular posts from this blog

Design using Standard Description Languages:The simulation model in VHDL

Image
The simulation model in VHDL After a look at concurrent signal statements in chapter 4.3, basic mechanisms of the language can be discussed in detail. Originally the language VHDL was developed for simulation only. A dis- cussion about the theory of operation of a VHDL simulator helps to understand VHDL modelling and simplifies the choice of suitable language constructs to describe hardware constructs. The topic simulation model has an emphasis on: • Driving signals; • Delta delay mechanisms; • Modelling of delay times. Drivers Every concurrent statement, including processes, causes an event responsible for the progress of a signal. Within the simulator there is a list containing points in time to schedule signal events. Such an entry in that list is called a transaction. This list is the basic information for scheduling signal values during simulation (fig. 4.22). A change of a signal value caused by an entry in that list, is called an event in that signal. If a new entry is the ...
Read more

EDA Tutorial:Place and Route in a Standard Cell Design Style

Image
Place and Route in a Standard Cell Design Style In the design of FPGA circuits, after the synthesis of the EDIF files, the compiling and programming of the FPGA device, everything is defined and the component is completely configured. With ASIC designs, there are two possible scenarios: • Delivery of the design to an ASIC provider in the form of a so called simulate d netlist (EDIF); • Place and Route of the design with one’s own tools, verification of the results, and delivering of the design as a geometrically exact GD S II File . For similar designs in industry the netlist version is frequently chosen, but here the second scenario which includes the bac k en d processing , the phys- ical design, will be demonstrated in more detail. This needs special software tools, which allow the mask design at the lowest geometry level, and tools for checking the generated geometries against the predefined design rules ( Desig n Rule Che c k , DRC ), and allow one to extract parasitics and el...
Read more

Overview of EDA Tools and Design Concepts:Major Classes of EDA Tools.

Image
Introduction In the next few chapters, we will discuss specific kinds of EDA tools. In this chapter, we provide an overview of the EDA tool world. There are several EDA-related concepts which are helpful to understand the EDA tools and the design process. These include: Design Views Hierarchy Design Chip Architecture Methodology Design Flow Tool Suites Nora of Sandbox, Inc., is meeting again with Andrea, an ASIC engineer who works for Fabless Design, Inc. Nora has asked to learn more about the use of EDA tools. Let us listen in on their discussion. Nora: Hello again, Andrea. Did you like the party the other evening? Andrea: Yes, very much. Sandbox has both outstanding tools and great parties. Nora: We seem to be continually developing new tools. I am a little unclear why that is. Tool Improvements Andrea: That's because each generation of semiconductor process improvements shrinks the size of the transistors and wires. The number of transistors and wires...
Read more