Overview of EDA Tools and Design Concepts:Architecture, Methodology, and Design Flow.

Architecture, Methodology, and Design Flow

Nora:

What do designers mean when they speak of chip "architectures"?

IC Architectures

Andrea:

That is more jargon. There are many ways to implement an IC design. The designer chooses a specific physical IC architecture to implement the design (e.g., GA, SC, FPGA, or custom). Do you know about those?

Nora:

A little—someone at Sandbox said they were different ways to make an IC. He emphasized the time-to-market issue.

Andrea:

That's right. Here, let me sketch you a picture of some IC architectures. (See Figure 4.3.)

Note the four different physical IC architectures. The block-based IC is usually a custom chip. The individual blocks may be custom logic, or memory blocks or microprocessors. The cells in the standard cell and FPGA chips may be many different kinds of gates. And FPGAs come in various flavors and styles as well.

The gate array is a fixed array, usually of the same complex gate. The gate array and FPGA chips come in fixed sizes determined by the manufacturer. However, the standard cell and block-based chip can vary as large or small as the application needs.

Also note that combinations of these architectures are common. For example, there might be some fixed microprocessor or memory blocks embedded in the FPGA. A standard cell implementation of some function might be just one block in a block-based chip.

Nora:

As I recall, the gate array, standard cell, and FPGA were all ways to simplify the design and speed the time-to-market.

Andrea:

That's right. We developed architectures and design aids for the most repetitive and tedious aspects in design.

Nora:

What do the designers mean when they talk about "methodology" and "design flow"?

04fig03

Design Methodology and Design Flow

Andrea:

Let me show you a comparison of design methodology and design flow. (See Figure 4.4.)

Note that Design Methodology is the sequence of design steps needed to implement a particular architecture. Design steps include entering a design into the computer, testing it, doing physical layout, and so forth.

If the physical architecture of the IC is different, the design steps may be different. For example, designing an FPGA requires different design steps from designing a standard cell IC.

A Design Flow is the specific set or suite of EDA tools used to implement the design methodology steps. The design flow is often a script calling out the tool and file details for each operation. Some of the methodology steps might involve more than one tool and multiple files. What I sketched here is a very simplistic overview. Real methodologies are much more complex and detailed.

Nora:

Okay, I think I get the general idea. Hugo explained the business differences, but these sketches help. Can you explain more about tool suites?

04fig04

Tool Suites

Andrea:

Okay. At particular points in the design sequence, we developed individual tools to aid manual design. Different groups created the tools independently of each other and at different times. Therefore, most point tools have different user interfaces, data entry methods, and data storage styles.

Some point tools were modified to work together and were combined into clusters called tool suites.

Nora:

Thanks, Andrea.

Comments

Post a Comment

Popular posts from this blog

Design using Standard Description Languages:The simulation model in VHDL

Image
The simulation model in VHDL After a look at concurrent signal statements in chapter 4.3, basic mechanisms of the language can be discussed in detail. Originally the language VHDL was developed for simulation only. A dis- cussion about the theory of operation of a VHDL simulator helps to understand VHDL modelling and simplifies the choice of suitable language constructs to describe hardware constructs. The topic simulation model has an emphasis on: • Driving signals; • Delta delay mechanisms; • Modelling of delay times. Drivers Every concurrent statement, including processes, causes an event responsible for the progress of a signal. Within the simulator there is a list containing points in time to schedule signal events. Such an entry in that list is called a transaction. This list is the basic information for scheduling signal values during simulation (fig. 4.22). A change of a signal value caused by an entry in that list, is called an event in that signal. If a new entry is the ...
Read more

EDA Tutorial:Place and Route in a Standard Cell Design Style

Image
Place and Route in a Standard Cell Design Style In the design of FPGA circuits, after the synthesis of the EDIF files, the compiling and programming of the FPGA device, everything is defined and the component is completely configured. With ASIC designs, there are two possible scenarios: • Delivery of the design to an ASIC provider in the form of a so called simulate d netlist (EDIF); • Place and Route of the design with one’s own tools, verification of the results, and delivering of the design as a geometrically exact GD S II File . For similar designs in industry the netlist version is frequently chosen, but here the second scenario which includes the bac k en d processing , the phys- ical design, will be demonstrated in more detail. This needs special software tools, which allow the mask design at the lowest geometry level, and tools for checking the generated geometries against the predefined design rules ( Desig n Rule Che c k , DRC ), and allow one to extract parasitics and el...
Read more

Overview of EDA Tools and Design Concepts:Major Classes of EDA Tools.

Image
Introduction In the next few chapters, we will discuss specific kinds of EDA tools. In this chapter, we provide an overview of the EDA tool world. There are several EDA-related concepts which are helpful to understand the EDA tools and the design process. These include: Design Views Hierarchy Design Chip Architecture Methodology Design Flow Tool Suites Nora of Sandbox, Inc., is meeting again with Andrea, an ASIC engineer who works for Fabless Design, Inc. Nora has asked to learn more about the use of EDA tools. Let us listen in on their discussion. Nora: Hello again, Andrea. Did you like the party the other evening? Andrea: Yes, very much. Sandbox has both outstanding tools and great parties. Nora: We seem to be continually developing new tools. I am a little unclear why that is. Tool Improvements Andrea: That's because each generation of semiconductor process improvements shrinks the size of the transistors and wires. The number of transistors and wires...
Read more