Electronic Design Automation (EDA)

Chip Mounting and Printed Circuit Board / Hybrid Design To analyse the working of the chip samples, some manufactured dies were mounted in JEDEC CLCC44 packages. The bonding plan fig. 26.17 has to be defined for that. The bonding plan defines the pins of the package. To use and test the chip an external circuit with LEDs, button, and some passive components is needed. This external circuit was designed in SMD technology on a printed circuit board of the size of a chip card fig. 26.18. The EDA tools used will not be described further here. A second variant of the dice was mounted on a thi c k film hybrid subst r ate , made in a process available at the University of Applied Sciences Offenburg. It has to be mentioned that the whole design and all process steps including the hybrid processes were made by students in projects at the above school [26.1], [26.2], and are now part of the actual engineering curriculum in Offenburg/Germany.

Place and Route in a Standard Cell Design Style In the design of FPGA circuits, after the synthesis of the EDIF files, the compiling and programming of the FPGA device, everything is defined and the component is completely configured. With ASIC designs, there are two possible scenarios: • Delivery of the design to an ASIC provider in the form of a so called simulate d netlist (EDIF); • Place and Route of the design with one’s own tools, verification of the results, and delivering of the design as a geometrically exact GD S II File . For similar designs in industry the netlist version is frequently chosen, but here the second scenario which includes the bac k en d processing , the phys- ical design, will be demonstrated in more detail. This needs special software tools, which allow the mask design at the lowest geometry level, and tools for checking the generated geometries against the predefined design rules ( Desig n Rule Che c k , DRC ), and allow one to extract parasitics and el...

Completion of the design with Pad Cells and Validation of the Entire Design The circuits developed lack any pad cells for the input and output signals of the chip. Selection of these cells is subject to considerations of the external circuit. This is output loading for driver cells, and for input cells the behaviour of the input signal determines which kind of cell has to be used. In the dice circuit, a Schmitt Trigger Input cell is used for the input signal derived from the button to obtain a hysteresis behaviour for slowly increasing signals. Bouncing of the button has to be suppressed by the FSM which processes the button signal and which synchronizes the signal with the internal clock. This functionality has to be respected during the design of the control FSM and is not part of the pad cell selection considerations. To be brief, there are no pad cells with anti bouncing characteristics. For all other input cells standard input pad cells are selected, most of them with an int...

Synthesis on ASIC Standard Cell Technology Synthesis with the target technology ‘ standa r d cell ’ (same is true for gat e array ) is not very different from synthesis with FPGA technology. The only difference is in the target library, which is built up from basic logic gates with ASICs in contrast to the more complex structured FPGA logic cells. So there are AND, NAND, OR, EXOR, etc. available in each ASIC library, but LUT cells are not. New are complex gates like AND OR INV gates (AOI gates) in different forms, which leads to some improvements in area and power consumption compared with basic gates, saving some interconnection wires in between the sub- gates too. The synthesis tool prefers to use these gates where ever possible. The gate usage statistics of the design mapped to an ASIC library with LEO N ARD O are shown in table 26.3. Area optimised complex gates are used quite often. The synthesized design now contains 225 cells (without GND), about the same as the design made ...

Synthesis and Emulation on FPGA The limitations of verification by functional digital simulation are quite obvious if the sound generation is involved. One cannot deduce from the t r ace s 1), what a melody tone ‘sounds’ like if the tone’s pitch is comfortable and the sound’s duration long enough. Also the ergonomics of button operation, the time constants used, and the run off times may be badly evaluated from traces on a screen. From this it is very important to synthesize this circuit on FPGA and emulate it there. As a prototype, all functions may be operated in real time several times and the reactions may be observed in many repetitions, something which is impossible in digital simulation because of the long run times. For educational purposes FPGA emulations have high value, because each student is able to verify his own design by reprogramming the FPGA. The result is easy to inspect for the instructor. In the practice of the courses we have the experience that even if all desig...

Verification by Functional Simulation Verification is carried out with a digital simulator. The simulation of the schematics may be carried out with Qui c ksi m (Mentor). Increasingly this program is being replaced by modelsi m (Exemplar, Mentor Graphics), a VHDL compiler and simulator. To use this simulator with Desig n Architect the netlist has to be generated in structured VHDL format, and in which the library components have to be taken from a VITAL compliant library. There is no quality difference in simulating with modelsi m as a VHDL simulator and a more symbol oriented classical simulator Qui c ksim . Delay times of instantiated gates, as far as they are included in the library, are taken into account. Figure 26.7 shows a screenshot of the modelsi m simulation of the dice counter FSM, the related stimuli script is contained in list 26.3. The building blocks are simulated one after an- other and differences from the intended behaviour have to be modified at the design entry le...

Implementation of the Design by Schematic Entry All schematics are designed and input into EDA using the schematics input tool Design Architect (Mentor Graphics) one after the other. Figure 26.4 shows one sheet with the central dice counter FSM circuit. The logic may be designed with classical logic design methods by hand or derived from the state diagrams using supporting programs, e.g., LogIC. This is done by further dividing the blocks into sub blocks until a design by hand is feasible and well known and proven circuits can be used. Verification of these circuits, sub-blocks and blocks is nowadays done by functional digital simulation. The result of this classical structured method is 230 gates, see table 26.1 for a statistics of the used gates. The result is now transformed in a netlist (e.g., EDIF) and available for further processing. Implementation of the Design using the High Level Language VHDL As an alternate design approach to schematics input the design is described b...

PCB Layout PCB Layout Overview Netlis t generation : From the schematic the netlist is generated by the EDA software. Layout means the placement of all components listed in the netlist and the routing of all electrical interconnection in defined layers between the pins of the components as described by the nets in the netlist. Figure 25.9 shows the layout design flow. P r ojec t library generation : In many cases there are components with the same electrical characteristics, but mounted in different packages. Figures 25.6 and 25.7 show examples, in which the same type of operational amplifier is available in a DIL package or in a TO5 package. For the layout process the user must therefore select first a suitable package. Thus the logic symbols of the compo nents must be assigned to the packages by defining the part number. This is done by choosing the available par t numbers from a library for a given device. If there is no part of this type available in the library, the user has to c r...