Trends:Semiconductor Trends.

Semiconductor Trends

As we have seen, the semiconductor industry includes several different players and types of ICs. The continuing smaller feature sizes have created larger problems. EDA tools help solve the IC problems. So IC developments have had great influence on the development of EDA tools. It is reasonable to ask, "What next?"

Many new design issues arise as the process dimensions shrink below 0.18 micron, and again at 0.90 micron. Performance, power, thermal design, and physical design are affected. New materials are emerging. These developments affect the transistor models and manufacturing rules used in the EDA tools.

The trends described below include:

  • Performance Design Issues

  • Power and Thermal Design Issues

  • Physical Design Issues

  • New Materials and Lithography

Performance Design Issues

Interconnect Delay. Thinner wires have more resistance and capacitance, which increases the delay through them. (See Appendix A.) A larger chip means that some wires will be longer—further increasing the delay. This increase in delay conflicts with the attempt to run the chip at faster speeds.

Lower Voltage and Smaller Transistors. A smaller transistor and lower voltage give a shorter delay (good—it switches faster). But it also makes a weaker signal (bad—more signal wire delay and sensitivity to noise).

Crosstalk. Rapidly changing signals on one wire can induce a transient signal on nearby wires. If many signals are changing nearby at the same time, the effect can be large. This simultaneous switching noise can cause signal delays and logic or memory errors.

Signal Integrity. Noise affects the integrity of the signal (how well it is defined as a "1" or a "0"). Noise comes from many sources (clocks, crosstalk, power, and ground lines, or chip leakage paths). Noise may cause signal delays, or logic and memory errors.

Clocks. With more functions on the chip, there may be hundreds of clocks running all over the chip. The noise generated by the clocks also affects the signal integrity.

RF Blocks. Radio frequency (RF) chips used to be separate ICs. Wireless applications are an increasing trend. Wireless circuitry embedded on the digital chip is also an increasing trend. RF circuits run at very high frequencies. The RF signals do not stay on the wires but can radiate throughout the chip. They may induce noise and cause memory upsets affecting signal integrity.

Power and Thermal Design Issues

Power Distribution. More transistors switching need more power. Power distribution to different logic blocks on the chip grows more complex. Thinner wires have more resistance, increasing the voltage drop to the blocks.

Electro-migration. With smaller wires, heavy currents can actually move metal atoms. This thins the wire even more, increasing the current density. Eventually a wire break results.

Thermal Distribution. With smaller feature sizes, power may be focused in dense hot spots on the chip. This affects the local transistors' speed and noise sensitivity. It can also cause mechanical stress and cracks in the wires or the silicon.

Physical Design Issues

Antenna Effects. Certain layout patterns can cause long unwanted wire stubs which affect the signal integrity.

More Wiring Layers. With more transistors, more layers of interconnect are needed to wire them together. Each layer of interconnect adds more vias and more potential manufacturing problems (as well as cost).

More Wiring Vias. Vias (pass-throughs from one wiring layer to another) are weak links in the manufacturing process. More vias mean more chances for a connection failure.

Mask Costs. With more layers, there are more mask costs. (Each DSM mask set now costs millions of dollars.) An error which requires a new mask set is very expensive in time and dollars!

Hot Electron Effect. The small dimensions can create high electric fields which accelerate electrons. These hot electrons can damage the transistor. This is a major reliability problem.

New Materials and Lithography

New materials. The use of silicon is being challenged as the all-purpose substrate for integrated circuits. Silicon is cheap and easy to process. Silicon Germanium (SiGe), Gallium Arsenide (GaAs), and Strained Silicon are better for high-speed circuits.

Silicon-on-Insulator (SOI). This is one way to reduce transistor delays and interactions through the chip substrate. (A layer of silicon dioxide insulates all the active transistors from the base chip.) SOI reduces leakage, power loss, and enables faster circuits.

Copper. This has replaced aluminum for faster interconnect wiring. New (low K) insulating materials have also been used to reduce interlayer capacitance for faster interconnect. These trends affect the EDA interconnect and switch delay models.

Finer Lithography. The optical lithography may come to an end, but scientists are looking beyond that. The trend toward further reduction of feature size may come from the use of X-rays or electron beams. New work is assembling patterns by directly moving molecules and even individual atoms. New EDA tools will no doubt be needed to deal with these developments.

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