Design using Standard Description Languages:Concurrent Statements

Concurrent Statements

The hardware description language VHDL differs from other programming languages because con- current and sequential statements are possible.

All statements within an architecture describe activities taking place concurrently. Part of those are the ordinary signal assignment, conditional and selective assignments, component instantiation, and the entire process. The sequence of concurrent statements in a VHDL text is not important. This reflects the general behavior of digital hardware, in which signal transitions occur in parallel.

Within a process the execution of statements is performed sequentially. This corresponds to the understanding of a classic programming language.

Concurrent Signal Assignment

Apart from their task of connecting components, signals can be combined with each other and form a part of combinatorial logic in this way. Simple signal assignments are:

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Next to the VHDL description of the full adder, it would not be a big problem to draw an equivalent circuit containing XOR, AND, and OR gates. However, this circuit would not be a result of an automatic synthesis. Synthesis has to meet a set of constraints and find a compromise. The result depends on the target technology and requirements concerning area and speed as well as periphery. Requirements such as fan out, driving capabilities, capacitive loads, or the availability of, e.g., XOR components, must all be taken into account. The answers to these questions decide what the circuit looks like after synthesis.

Conditional Signal Assignment

The simplest way to assign a signal conditionally describes a multiplexer (fig. 4.16):

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Selected Signal Assignment

This type of signal assignment allows only one condition to be specified. The result of this test determines the source and target being connected.

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Conditional signal assignments can be expanded to realize complex hierarchical multiplexers (fig. 4.17).

Contrary to a conditional signal assignment, individual tests (WHEN 0, WHEN 1, ...) describe no hierarchy. They have the same priority and exclude each other mutually. All elements of the set of values the condition can take (see examples 0 ... 3) must be enumerated.

The last test (WHEN OTHERS) can combine all remaining possibilities.

It can not be assumed that mutual dependences of conditions will be detected by the synthesizer. Having dependences, it is recommended that a selected signal assignment is inserted in order to avoid redundant logic.

The last ELSE statement carrying no condition should handle all conditions not covered so far. Otherwise a situation could occur in which a new value would not be assigned to the output. This means that during synthesis feedback paths or asynchronous storage elements would be inserted

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The following example shows two different ver- sions of implementing the functional description in figure 4.19. Both solutions produce the same results in simulation and synthesis (figures 4.20 and 4.21).

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