EDA Party—Users and Tools,System Design and Logic Design

EDA Party—Users and Tools

Nora Newbie is attending a party hosted by her new employer, an EDA company, Sandbox Tools, Inc. Sandbox is celebrating the release of a new company product, and several customers are at the party.

Nora is a recent college graduate with some public relations and marketing background. Let us listen in as she meets some new people. Her supervisor has just introduced her to Donna, an EDA tool developer with Sandbox.

Donna:

Hi, Nora, welcome to Sandbox Tools.

Nora:

Thanks, Donna. This is all new to me. I am not even sure what the company does. What do you do here?

Donna:

The company develops EDA tools that engineers use to design ICs. I help write the programs, test them, and help our first customers try them out.

They suggest corrections or improvements that I make to the program. Then I retest the program, and the users try it again, until we get it right.

Nora:

So, are the EDA tools similar to my word processor?

Donna:

Somewhat, except they are specialized for electronic hardware design, instead of document creation, and with lots more data. EDA tools help engineers enter design ideas, verify that the ideas work, and check for errors. With millions of transistors on a chip, there is a lot of room for error.

Nora:

The EDA tools must really be important. Did you work on this new product?

Donna:

Yes, I put in many long hours. It is very satisfying to see the program finally working and getting used by the engineers.

Nora:

Which engineers use our tools?

Donna:

Engineers design ICs for communications equipment, industrial controls, military systems, and consumer electronics. EDA tools are for primarily system engineers, logic designers, verification engineers, ASIC designers, and layout designers.

Nora:

I didn't realize there were so many types of engineers. Are they really all our customers?

Donna:

Yes, and those are just some of the electronics engineering disciplines.

Nora:

What do they all do?

Donna:

Well, some of them are here at the party. Why don't I introduce you to them and they can tell you themselves. They all use EDA tools.

Nora:

That sounds good to me.

System Design

Donna:

Hey, Sam. This is Nora, who just joined Sandbox in the PR and marketing group. Can you tell her a little about what you system engineers do?

Sam:

All right, Donna. Hello, Nora. Well, I work for SysComInc, a systems company that makes communication equipment for the Internet.

System engineers are like architects who provide a set of plans to a construction company. We help determine a product's requirements, explore ways of making it, and define all needed components. Then we make a model or prototype of the design. ICs are part of electronic products, so we end up specifying or designing those as well.

Nora:

How does an EDA company like Sandbox Tools relate to all that?

Sam:

Sandbox makes a system modeling tool which we use to check out our ideas. Modeling is a little like those real estate virtual tours on the Internet, where you can "walk" through a house. We model the riskiest parts of the design using your software tool. It saves us months of building a hardware prototype design.

In communications, many people may try to access a particular website at the same time. If our product takes too long to handle each access request, the customers go somewhere else. So we model the network loading (how many customers we can support per second). That tells us if our design approach will work.

Nora:

The tools can predict if it will work or not?

Sam:

Most of the time. Some parts of the design are complicated and hard to prove out any other way. It is fun to design things that have never been done before or were previously impossible. When you finally get your product to work, it is very satisfying.

Nora:

Yes, Donna said that about her work, too. Do you design ICs as well?

Sam:

I don't, but I sometimes describe what capabilities a chip must have for a specific product. Let me introduce you to Luigi, who is a logic designer, and Andrea, an ASIC engineer. They can explain about ICs better than I can.

Logic Design

Nora:

Thanks, Sam. It's nice meeting you. Hi, Luigi.

Luigi:

Hello, Nora. What can I do for you?

Nora:

I'm new to Sandbox Tools, and I understand we make EDA tools for IC design. Can you tell me about that and what you do?

Luigi:

Sure, Nora. I am a logic designer, and I work for Federal Semiconductor, a company that makes ICs. We are one of your customers. What we do is take the IC requirements from a customer or system designer like Sam. Then I design logic which implements the operations that he needs the IC to do.

Nora:

What do you mean exactly by logic?

Luigi:

Well, for example, supposing I want to start my car.

A. I have to have the key, AND

B. The car has to have gas, AND

C. The car has to be in "Park."

If all of these things are true, the result is that I can start the car. If any one is false, then I can't start the car.

Think of it as a "decision box" with three inputs: A, B, and C. Think of the decision box having an output D, which is being able to start the car. D is true only if A AND B AND C are true. If any one of them (A, B, or C) is false, then the output will be false. That's logic.

Nora:

That's all there is to it?

Luigi:

Well, there are a few types of logical decisions. For example, supposing you, Sam, and Donna all have keys to my car. Then Nora OR Sam OR Donna could drive the car.

Think of another decision box—again with A, B, and C inputs. A is Nora being at the car, B is Sam at the car, and C is Donna at the car. This time, the output result, D, is that the car can be driven. D is true if any one of the inputs A OR B OR C is true.

We can make electrical circuits that make decisions just like the boxes. These logic circuits are called gates. What I just described was a logical AND gate, and a logical OR gate.

We can also make circuits that remember a value, whether it was true or false. Think of a light switch that you switch on or off. It stays where you last set it, either on or off. We can make memory circuits that behave the same way.

Most system problems can be described as a sequence of logical decisions. We can implement those with logic and memory circuits. I design the logic so that the inputs are transformed into outputs as specified.

Nora:

So what do you end up with?

Luigi:

A list of different logic gates, memory circuits, and the wires (or nets) that connect them. It's called a netlist.

Nora:

Okay, I follow that—but where does the IC come in?

Luigi:

The IC is full of transistors used to make logic gates and memory circuits.

Nora:

So you choose the logic gates and the connections—is that logic design? Do you use any EDA tools?

Luigi:

Oh yes. There are EDA tools to help the poor logic designer. We have tools to enter the design ideas into a computer using pictures (graphic symbols) or words (text). We describe the logic gates and the connections. There are various checking tools to catch entry errors.

We also have tools to verify that the logic does what we expected. Verification typically takes over two-thirds of the project design time. It is iterative—design, verify, re-design, verify, and so on. However, the Sandbox people have some new verification tools that should speed things up.

Nora:

There seems to be more verification than design.

Luigi:

It can be tedious, but it's like being a writer or artist—when I finish it—getting it to work—I feel a real sense of accomplishment.

Nora:

So how does your netlist become an IC?

Luigi:

You catch on quickly. You have noticed that this whole design process is a sequence of steps from idea to chip. Andrea, can you explain to Nora how my netlist becomes an IC?

ASIC Design

Andrea:

Sure, Luigi. Hi, Nora. I am an ASIC engineer, and work for Fabless Design Co., an IC design company. We design ICs, but use an external foundry to manufacture our chips.

Nora:

Hello, Andrea. What is an ASIC and what does an ASIC engineer do?

Andrea:

Well, suppose you build a custom house where every part (door, window, etc.) is custom-made for you. Another approach is an architecture that uses standard-sized, prefabricated doors, or windows. With this semi-custom architecture, you can get all its parts from a standard catalog. So you still have some choice, but not the total flexibility of full custom. However, the semi-custom approach is much faster.

ASIC stands for Application Specific Integrated Circuit. ASICs are ICs designed using a semi-custom architecture. The architecture is an array of standard-sized circuits. A shorter design time is possible using libraries of standard-sized predesigned circuits (gates or cells) that fit into the array. A shorter design time gets to market faster, which everyone wants. There are several kinds of semi-custom ASIC architectures.

Nora:

So what exactly do you do?

Andrea:

In the house analogy, a paper plan may call for a 30-inch window. Then the architect would select a real physical window from the catalog (for example, ClearPane model 53, birch, dual pane, tinted glass).

For the IC, I design the logic using standard parts from libraries of gates or cells. The logic design is still like a set of architect's detailed plans at this point.

After completing the logic design, I transform it into a chip design that can be manufactured. Transforming (or mapping) the logic design to a real library of gates and memory elements is called synthesis. I can do this tedious job manually or with an automatic EDA synthesis tool.

The tool helps optimize the design for chip area, power, performance, and so forth. After running synthesis, I check to make sure that the logic has not changed and that all electrical rules are met.

After that, I turn the design netlist over to a layout designer. Let me find someone to explain layout to you.

Physical Layout Design

Let's see, I think Larry is here, and he is a layout designer. Hey, Larry. This is Nora, who just joined Sandbox. Can you please explain to her how you do your magic?

Larry:

Sure. Hello, Nora.

Nora:

Nice to meet you, Larry. Thanks, Andrea.

Larry:

I work for Fabless Design Co., same as Andrea.

After Andrea has a netlist with real physical information, I do physical design steps called layout. These steps include physically locating or placing the many logic elements on the chip. Then the wiring between logic elements must be planned or routed.

Layout is all about minimizing chip area and interconnect wire lengths. The time delays through the gates and wires limit the speed of the chip. The shorter the wires, the less the delay and the faster the chip. The chip may be too slow due to a critical signal with a long interconnect wire.

Nora:

How much delay are we talking about?

Larry:

Nanoseconds... that's a billionth of a second. Light travels very fast. It could circle the earth eight times in a second. It can travel about one foot in a nanosecond. A personal computer typically executes one instruction in less than a nanosecond. So on a half-inch IC, we are worrying about fractions of nanoseconds. Electrons don't travel at the speed of light in wires, but they are pretty fast.

Nora:

These are really short times...

Larry:

Very short indeed. In addition, as chip features become smaller, the time delays become even more critical. The layout of the wires is very important. And now with things closer together on the chip, layout engineers have to worry about many new factors besides area and timing.

Layout consists of placement and routing. Using an EDA placement tool, we place the gates or cells at locations on the chip. Those cells with the most connections between them are placed close together.

A good placement enables short wires between the cells. It is similar to routing water pipes in a home. You want the water pipes to have the shortest path from the heater to the faucet, so you get hot water quickly.

After all the cells are placed, another EDA tool routes the wire connections between the cells. Sometimes I have to change the placement repeatedly to improve the wiring.

The EDA placement and routing tools are not as smart as an experienced human designer. With literally millions of transistors on a chip, however, the tools do most of the layout. Nevertheless, sometimes we must intervene manually to complete a layout.

Nora:

Okay, so the placement affects the routing and the routing influences the placement? How do you know when you are done?

Larry:

Basically, when all the wires are routed and no critical signal wire is too long. (And all the other complex factors pass checking.)

Placement and routing tools try simultaneously to minimize several factors. These include the area, wire lengths, the number of wiring layers, and vias (layer-to-layer connections). Here, let me sketch this on a napkin for you. (See Figure 1.4.)

Larry:

See, the IC is built in layers. I didn't show the transistors, but the transistors are on the bottom layers on the chip, and the wiring is above. I drew only three metal wiring layers, but there might be four or six or more. Insulating material separates the wire layers. The only connection between wires and the transistors are little vertical metal posts called vias. You can see that electrons traveling between transistors may have to go along several wires on different layers, and through several vias. That is the routing problem.

After successful place and route, I turn the design back to Andrea, the ASIC engineer. She runs all kinds of analyses, such as timing, performance, power, area, thermal, and so forth. Then she runs all kinds of manufacturing design rule checks. These include things like sizes of transistors, wires, spacings, vias, and so forth.

Nora:

I didn't realize the errors were so costly! No wonder there are so many checking steps.

Larry:

Yes, and we have more checks required every time we improve the manufacturing process and things get smaller. New kinds of problems show up and the EDA tools have to adapt and check for them. New EDA tools are being developed all the time to keep up.

Nora:

What happens after all the checks are done?

Larry:

All the placement and routing information overlays the base chip. The base chip has all the bottom layer transistor information, and the input/output (I/O) pads. The final physical operations involve merging the design layers onto the base chip layers.

Then we create a final design database with all the information on it. A mask-making shop uses the final database to create the masks for the IC manufacturer.

This database file used to be stored on a magnetic tape, and the tape was sent to the IC manufacturer. The step of creating a final clean design database is still referred to as tapeout, and is still a really BIG event. The company may announce the new product and often celebrates with a party.

Nora:

So you are all involved in taking a system product from idea to an integrated circuit chip? And there are EDA tools at just about every step?

Andrea:

That's right.

Nora:

And I suppose there's another whole series of steps to actually manufacture the integrated circuit?

Andrea:

Right again. And another party when the first manufactured chip (first silicon) works.

Nora:

Okay, I will save those questions for another party. I have to digest what I heard here before I can learn any more.

Sanjay:

(Nora's supervisor) You asked yesterday about the benefits of EDA. Do you know some now?

Did You Know?

Correcting an IC error after manufacturing is very expensive and time-consuming. It may cost millions of dollars and take up to a year. Companies have gone out of business because of deadlines missed due to a chip error.

Designers need to be sure everything is right before going to IC manufacturing. EDA tools warn them of errors (such as a missing connection) and power, timing, or thermal problems.