Hardware/Software Co-Design:System on Chip Designs (SOC)

System on Chip Designs (SOC)

In systems on a chip (SOC) one expects today not only a processor core and dedicated application- speciﬁc electronics, but increasingly also sensors, similar circuits, and possibly even micro- mechanical components. The chip may contain not only the functionality of the printed circuit board but an entire system. Examples are contactless RF ID tags, sensors with integrated evaluation electronics and several smart card applications. A high degree of integration together with simultaneous mass production leads to low prices, and the impact on the consumer market is accordingly large. There are many new products on the horizon, the market for ID tags alone is gigantic and already in start up.

Concept and Speciﬁcation of SOC

The design of a SOC puts highest demands on the designer, not least because he has now to under- stand more technical disciplines than ever before and combine them in one model consistently. The speciﬁcation of the analog blocks is one order of magnitude more difﬁcult and does not follow a systematic methodology compared to the digital blocks. In the analog area, completely different terms are used, and the results are not as reproducible as in digital domain. So physical environmental conditions such as temperature, voltage supply, and process tolerance have an important inﬂuence on function and have to be considered or compensated. Circuits which work in the high frequency regime should fulﬁl further requirements, which may be difﬁcult to test. It is therefore nearly impossible to write a formal speciﬁcation for such a system, even more to process it in an EDA system automatically.

Usually analog cells are speciﬁed and qualiﬁed separately and later transferred as veriﬁed IP cores to the SOC design. Proceeding further in the development, they were described by behaviour models, perhaps in VHDL-AMS. Analogue IP, such as A/D converters, reference cells, or temperature cells are offered by specialized IP providers, e.g., see the CircuitWare Library by Dolphin Integration.

Micro-Mechanical Systems: Combined Digital, Analogue and Mechanical World With the inclusion of micro-mechanical functional blocks into a SOC, the highest complexity is reached. At present there are only few successful examples of one chip products. The same conditions apply to multi-chip modules in which the micro-mechanical chip is combined with a conventional CMOS IC on a ceramic substrate. The hybrid version is today more cost effective than the monolithic design, because the micro-mechanical process is in many cases incompatible with the standard IC process. Even if the processes are made compatible, many researchers are working on this topic, the questions of yield and silicon area consumption are still not answered satisfactorily. Mass applications such as the acceleration sensors for car airbags are nearly everywhere built as hybrid components.

For modelling these systems the mechanical components and their behaviour also have to be included into the simulation. For such applications, perhaps as a later follower of the famous SPICE simulator, VHDL-AMS (AMS stands for Analogue Mixed Systems) is used as a new standard modelling language, allowing a uniﬁed speciﬁcation and simulation style for the analogue as well as for the digital world. VHDL-AMS will be described more, in detail, in another chapter. With this standard simulation language analogue and micro-mechanical components can be included into a functional system simulation in a consistent way.

SOC Simulation with VHDL AMS

The simulation of a complex SOC requires the co- operation of several engineering disciplines and puts high demands on the modelling quality. Everybody who uses SPICE knows that the accuracy of the results depends mainly on the extent reality is described by the models. This requirement is already difﬁcult to accomplish with purely electrical circuits and becomes even more difﬁcult with micro-mechanical components. A solution may be a separation of the tasks and moving of the modelling task completely to the cell-provider, who has worked out the cell in a detailed and expensive development and qualiﬁcation process. The cell provider is the only one who can guarantee the speciﬁed characteristics.

In further development steps simulation has to be applied at every level. The existence of an analog cell will not disturb further, as far as the outputs of these cells are modelled consistently. Modern VHDL simulator tools such as modelsim have no problems with showing analogue signals in their trace windows, VHDL AMS support is already there.

The challenge:

Testing of Systems on Chip

Testing of a SOC containing analog and micro- mechanical components together with digital electronics is a challenge. A functional test is in many cases only possible after complete assembly in a housing. In order to obtain a better yield, component tests at the IC level are very important.

As an entrance to the chip, the JTAG concept is generally accepted. By means of a few additional pins, used eventually as a secondary function for existing connections, all internal conditions of the chip are accessible and can be set or read. This philosophy is described in other chapters more in detail.

Analogue subsystems usually cannot be tested with JTAG; additional measures are required. Common is the integration of stimuli generators into the chip for the analogue components, whose response can be selected and read out via digital signals. These tests are limited usually to the demonstration of the general function of the cell, less to the compliance to the speciﬁed values. But they are useful, too, for self-testing of the chip in an application. Detailed testing can only be done on the complete, assembled system.

The tolerances of analogue systems are frequently compensated by adjustment and calibrating. Trimming (e.g., through laser ablation of structures on the chip) is common and established for analog components; for a SOC, however, it is a signiﬁcant cost factor. To avoid trimming, the intelligence of the integrated processor can be used to compensate tolerances by calculation. The measured calibration values may be stored digitally and used with each measurement to improve the results. Such a system may be cheaper than a laser trimmed version. Although there is a digital processor added, the development costs are spent only once. Trimming has to be done with each unit. In this way, process tolerances, as well as temperature inﬂuence on sensors, can be compensated to high quality, it would be easy to use and have a calibrated output.

Such a concept needs consistent logistical and measurement techniques during manufacturing, but allows multi-dimensional compensation and service quality. The processor core may be used to add communication facilities to the SOC, allowing it to interconnect directly to networks (CAN) and providing standard digital interfaces to thumb analogue sensors. Via these interfaces self-tests may be initiated, using the abovementioned stimuli generators, providing signal integrity, which is needed for present day complex, highly networked systems. These so called intelligent sensors will be the ﬁrst signiﬁcant commercial market for SOC.

Example Design of a System on Chip

To demonstrate a system on a chip design, a development made in the institute of the author, called ‘Thermologger’, will be described. This is a smart card which is able to record or log temperature from hours up to years. All functions including storage are integrated on one chip. Applications are in the area of food transport, medical transport, temperature monitoring of rooms, as well as in agriculture and planting.

Temperature is measured with an integrated temperature cell, converted to digital form and stored in a static CMOS RAM. For activation, as well for reading out the stored data the card is inserted into a reader. The microprocessor core in the SOC communicates with the reader which is connected to a personal computer PC via a serial interface. The PC controls the communication via passwords and stores conﬁguration data such as activation date, naming of application, period of measurement, etc., on the card. After data collection, the card is read out by the PC and the data measured may be represented as a proﬁle, a graph, or in textual form. The internal chip RAM is able to store about 7000 measurements, even more with data compression techniques, which is enough for most of the applications mentioned.

Control of data acquisition, of communication protocol, and the data compression is carried out by the integrated digital processor core. The core uses a built in BIOS stored in the ROM, which contains the driver for the periphery functions as well as the communications protocol engine. After connection to the PC the application routines are downloaded into the RAM, so the main program is not stored in the ROM but downloaded by activation and then executed. The main part of the software is in this way very ﬂexible and allows one to adapt the system to very different applications.

After activation of the system it goes into a power down mode in which all functions are switched off, except for an interval timer which has been conﬁgured beforehand during activation. After the pre-programmed intervals of minutes or hours the system awakes and performs the next measurement. This is repeated until the memory is full or the smart card is inserted into the reader station. Because of the low power consumption during power down mode and the short active phases of measurement, a small battery is able to supply the SOC for more than a year.

A picture of the chip is shown in ﬁg. 7.14. A mixed block design style was used in a CMOS 0.7 standard cells technology provided by ES2. The RAM memory cell is the largest part of the chip. The processor core FHOP_16 is to be seen as hardIP down right, the ROM completely on the left. The remaining electronics was dissolved in its hierarchy and ﬂattened in a standard cell style.

The version shown does not yet contain the temperature sensor, which will be integrated with the next generation, together with an inductive inter- face, which allows a wireless communication with the chip and so a hermetical sealing. A commercial use of this real ‘one chip design’ is intended in future.

In this system, only the BIOS programs are developed in a real hardware/software codesign method- ology and veriﬁed by functional simulation with the VHDL-simulator modelsim. The application program was developed, after the integrated circuit was already available. This was possible because of the download feature of the chip, allowing to implement programs into the RAM via the communication interface during runtime. The software uses several hardware-interrupt levels and software interrupts for the BIOS routines. The development took place in close interaction with the development of the reader and controlling PC-program.

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