Synthesis:Technology Mapping.

Technology Mapping

Mapping to the target technology is the process of implementing the technology-independent, but optimized, boolean network, using the gates available in a vendor-specific library (e.g., ASIC or FPGA).

When making the choice, specification limits such as speed of operation and area consumption must not be exceeded. This step in the work flow terminates synthesis, it should not alter the structure of the circuit significantly. The algorithms perform the task of implementing high speed gates along the critical path and, on the other hand, use gate combinations optimal in chip area otherwise. The libraries representing the target technology should be easily exchangeable for the user. At the same time the algorithms must handle the fact of li- braries often not offering the same choice of gates.

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Libraries

Libraries typically contain a large collection of gates (inverter, NAND, XOR) and sequential elements (flip flops). Each element receives a value assigned which specifies the area of the gate (measured in μm2, unit pattern sites, or in multiples of the area of a basic inverter or NAND gate). A percentage of the wiring area is often assigned as well. Additional parameters describe the timing behavior of the gate, especially the delay between input and output and the effect of possible loads. A popular delay model [6.2] identifies three parameters for each gate:

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where D is the resulting delay from input (i) to output (g), A is the delay with no load, B is a factor which specifies the delay per unit load, and C is the number of unit loads which the gate drives. Indices can be necessary when the propagation delays from individual inputs to the output of the gate are not identical. They can be omitted when the propagation delays from the inputs to the out- put are all the same. Figure 6.32 shows symbols of some library components with the equivalent  circuit structures employing NAND2 gates and INVERTERS. The consumption of real estate is expressed as multiples of a unit area, the parameters of a unit delay module are presented as well

Mapping

Prior to the mapping process the optimized technology-independent boolean net is converted to a form which contains only special basic functions. Often basic functions are a two-input NAND (NAND2) and an INVERTER. The library, too, keeps an equivalent representation made up of basic functions, the so called pattern. Having an element of a higher complexity, e.g., a NAND4 gate, several equivalent representations, all stored in the library are possible (fig. 6.33).

Limited to the basic functions, there are, at times, several different descriptions. Each could be used by the mapping algorithm as an initial network.

In the next step the network is significantly reconstructed in a way which leaves no branches (fig. 6.34). All outputs, including the new ones made by the rip up step, form a starting point for the mapping algorithm.

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At such a starting point each node is compared with all patterns in the library. If there are several equivalent library elements the figures of merit of area or delay decides which one should be used to provide an optimal result under the bottom lineSynthesis-0052

There is at least one trivial solution because all basic functions are, at the gate level, part of the library. Suitable library elements for the branch having the starting point 3 (see fig. 6.34) are shown in fig. 6.35. Two solutions are possible. The solution according to fig. 6.36a is the one preferred if the assumed time-critical path has to be minimized, since the NAND2, compared to NAND3, offers a better propagation delay (fig. 6.32). The second alternative in fig. 6.36b, however, shows a smaller chip area.

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