The Concept of Electronic Design Automation:Development steps

Development steps

In this section we will work out what particular tasks are required for the development of an application speciﬁc integrated circuit (ASIC) and what a reasonable ﬂow (or sequence) would look like. Common terms are design steps, and design ﬂow.

Within the Y chart we can identify the start and end points of the design process. We start at the overall speciﬁcation and we want to reach the center of the Y, – more precisely, ﬁnd the lower level of the geometric representation which is the set of polygons – as those represent the data needed for manufacturing.

We do have a certain amount of freedom in how to traverse through the Y chart. As mentioned above, we have seen that a direct translation from behavior into geometry will be difﬁcult – if not im- possible – at the outer levels. It is more appropriate to partition and structure the circuit ﬁrst. A few examples will show us that effort and data volume will grow if we walk down the behavioral axis. EDA can help by turning over to a computer the time consuming tasks and creating the vast amount of data. EDA tools will automatically generate the lower abstraction levels. Within the Y chart the migration to the structural and geometrical views will happen earlier (at an outer level) compared to a manual ﬂow.

The design steps mentioned below are typical for a design ﬂow of an integrated circuit. In this section we will not differentiate between manual and automated processes.

will behave at its pins or interfaces. This description must capture the logical behavior, electrical parameters, and environmental conditions. The latter typically being ranges of temperature and supply voltages within the chip are supposed to work. Electrical parameters are clock frequencies, timing behavior (minimum and maximum delays), and latences (number of clock cycles that may lapse until the chip must show a response to an input signal). Priorities may vary, depending on the segment of the application: handheld devices, in particular, have a tight power budget, as they may drain power from a battery, and may also have size and weight constraints, usually not critical for ﬁxed devices with access to the power grid. A good speciﬁcation completely captures the necessary behavior of the circuit (i.e., ‘every chip showing this behavior will work in the target application’), but does not impose constraints or give hints of how this functionality can be implemented.

Today there is no standardized language for sys- tem speciﬁcation. We often see a combination of timing diagrams, free text, and ﬁgures. Usage of classical programming languages such as ‘C’ enjoys growing acceptance, but a behavioral style of VHDL or Verilog is also common. Analog behavior is more difﬁcult to capture because of non-standardized terminology and measurement techniques.

Within the context of this book the chip speciﬁcation is the interface between IC development and system development. It can be seen as a duty book and captures what the design process has to aim at. After ﬁrst samples of the chip have been manufactured they will be compared (and qualiﬁed) against the target speciﬁcation, and potential mismatches (ideally there are none) must be understood and justiﬁed. The target speciﬁcation will then turns into the ﬁnal speciﬁcation and become the defacto documentation for all potential users who aim to use the particular chip in an electronic system.

A comprehensive speciﬁcation will also describe the measurement setup needed to verify a certain behavior. A common source for project delays and exploding costs is incomplete speciﬁcation. Un- fortunately, complete capture of the speciﬁcation is a much more difﬁcult and time consuming task than it may appear at ﬁrst sight.

The Algorithmic Model

This description makes early decisions about the architecture of the chip. Basic elements of an algorithmic model are operations like add, multiply, Boolean expressions, conditional expressions (if- then-else constructs) and memory functions. At this level we do not yet impose the sequence of the individual operations (this will become the scheduling process) and no assignments of the op- erators to physical resources like adder, multiplier are made (referred to as allocation).

The algorithmic level of a functional description is similar to a computer program and can be captured in a programming language such as ‘C’. Hardware description languages like VHDL or Verilog are also appropriate. The choice of a certain language will be driven by the availability of veriﬁcation tools and the methodology of how to transform the algorithmic level into the register-transfer level. If written in ‘C’, the model can be directly com- piled into an executable program allowing faster veriﬁcation than in case of VDHL and Verilog, which require the use of a simulation program. On the other hand, VHDL and Verilog still have an advantage if the algorithmic model is to be trans- lated into the register transfer level by means of behavioral synthesis (despite some recent progress in C synthesis).

The Register Transfer Level

Whilst the algorithmic description identiﬁes op- erations needed to implement the desired functionality, the register transfer level goes one step further and schedules those operations into certain clock cycles. If necessary or desirable, complex operations such as multiply can be split into several clock cycles. This allows for implementing the desired function with less and cheaper hardware at the cost of reduced performance, since it will take longer to perform the whole operation.

A ﬁnite state machine is needed to control the ex- ecution of the individual operations. This machine can be described by means of a state diagram, tabular form, or as a software program. Once the state machine has been deﬁned, the sequence of the operations is frozen.

The concept of sequential execution of the individual operations requires registers. These are memory elements capturing an input value at the active clock edge, and storing that value until the arrival of the next active clock edge. For each clock cycle the status of the circuit is completely described by the logic values stored in the registers. The status of the chip will change at the next active clock edge. A transfer function can be derived describing the next state as a function of the current state, thus the terminology ‘register transfer’.

To corroborate the difference between algorithmic level and register transfer level let us consider a serial 16 bit multiplier. Functionally multiplication requires a number of add operations. A parallel multiplier will execute all 16 add operations si- multaneously, whilst a serial multiplier executes them one by one in subsequent clock cycles. The advantage of the serial approach is that just a single adder is required in hardware. In contrast, for the parallel multiplier 16 adders must be provided in hardware leading to a larger circuit and hence to increased cost. A cost aware designer will, therefore, choose the serial version if performance is not critical and there is enough time to execute the add operations sequentially. He would make use of the more expensive parallel multiplier if the performance constraints mandate that.

The left hand side of Figure 2.2 shows the algorith- mic model of the multiplier expressed in VHDL, and on the other side we see the correspond- ing RTL model 1). The construct WAIT UNTIL CLK’EVENT AND CLK=‘1‘ speciﬁes that the next operation is to start with the rising clock edge: If the corresponding bit in the input register B is logic one, the content of the input register A will be added to the accumulator. The ﬂow is governed by the variable COUNT (in reality a 4 bit counter). It is initialized to the value 15 and decremented in each clock cycle. Once the counter value reaches zero the multiplication is complete and the content of ACCU can be transferred into the output register C.

Logic design

Going further down on the behavioral axis, the next step will be to decompose the operations into Boolean equations. However, state of the art design ﬂows bypass this step by transforming into the structural representation. This transition is referred to as technology mapping and the Boolean equations are replaced by physical gates and their interconnects.

The decomposition of an addition into Boolean equations is demonstrated in Figure 2.3. It can be seen that long and awkward expressions result. To avoid needless writing, common terms can be shared and be stored in internal variables. For instance, the carry bit can be expressed as a func- tion of the inputs A(N), B(N), and C(N − 1), the previous carry bit. Such a representation would immediately lead to a ripple carry architecture as shown structurally in Figure 2.3. An alternative realization is a carry look ahead architecture hav- ing the same Boolean equations but a different implementation of the carry path [2.9]. These implementations differ in their need for hardware resources and gate delays. An engineer (or a proper design tool) will choose a particular type depending on both performance requirements and the set of available cells. Standard cell libraries often contain a special full adder cell comprising all logic for the carry bit and the sum bit. A ripple carry architecture can be built from just this single cell type, as demonstrated in the example above.

In a modern design ﬂow logic design is automatic and will be done by logic synthesis tools. To simplify electrical and geometrical design (layout) of digital ASICs (Application Speciﬁc Integrated Circuit) basic cells are taken from a cell library rather than designing individual circuit elements. Logic design has to assist in this process: If the Boolean equations are written in such a way that all operators have a corresponding cell in the target cell library, then their mapping to an electrical design is straightforward. For instance, if the target cell library does not contain OR gates 1) then the Boolean expressions ought to be written in such a way that all OR operators are transformed into NOT and AND operators. This implies that logic design is only meaningful after the selection of the target cell library, and the best way to express the result of logic design is a structural view. This can be described by either schematics or a netlist capturing the instances of the basic cells and their connectivity.

Transistor Level Circuit Design

The mission of circuit design is the transformation of a logic description into a transistor level netlist and the sizing of the transistors. Figure 2.4 shows the transformation of a logic symbol into the transistor level representation. A CMOS technology provides two types of transistors: n-channel (NMOS) and p-channel transistors (PMOS). Their primary parameters are channel length, channel width, and oxide thickness, and those mainly in- ﬂuence the I V diagram, the relationship between the drain current and terminal voltages applied.

One of the goals at this level is to determine the transistor parameters such that the desired electrical properties – primarily performance – can be met. The target technology (the manufacturing process) sets certain constraints:

• The oxide thickness is ﬁxed in a particular tech- nology; it cannot be changed by the designer.

• Channel length and width must be chosen above a certain minimum boundary.

For digital circuits it is advisable to set the channel length for all transistors to the minimum value supported by the target technology. This will both maximize performance and minimize the area of the chip (and hence cost). The optimization space is, therefore, limited to selecting of a value for the channel width. Narrow channels cause currents to decrease but also delays to go up, whereas wider channels will lead to higher performance at the expense of chip area, and power consumption, of course.

Normally ASICs are built from gate array or standard cell libraries according to a semi-custom design methodology. Rather than optimizing at transistor level, pre-designed, standardized cells will be (re-)used, and, placed within a schematic diagram or instantiated within a gate level netlist. To allow for the speed vers area trade off modern cell libraries offer several speed versions for the same logic function. They differ in the size (or strength) of the internal transistors 1). For instance, a NAND function can be offered with strength 1, 2, 4, 8, 12, ... Whilst the designer, or the EDA tool cannot pick the individual optimum size, he can choose a cell that comes closest. Therefore a semi-custom design ﬂow will lead to a circuit which is slightly larger than the smallest possible chip. This is the price you have to pay for design time and effort reduction.

Transistor level design is still being done for analog circuits and the design of standard cell libraries. For the latter, optimization is less of an issue – the library is to enable a number of chips, therefore no particular performance goals can be set. Characterization of all cells is the major task: A very good delay model must be provided for every cell, sufﬁciently accurate within a wide range of operating conditions. These are input slew rates, output loads, temperature, supply voltage, and manufacturing tolerances. Careful characterization drives the cost of the development of a new standard cell library. Nevertheless, cells in a library will be reused so many times such that the effort is well justiﬁed.

Polygon Pushing (Layout)

Once the size of the transistors and their intercon- nects have been ﬁxed, the transformation into the geometric domain can start. Here the mission is to ﬁnd a geometric placement for the polygons that build the transistors or cells and their interconnects in such a way that the silicon area is minimal. The result is commonly referred to as layout or physical design. Figure 2.5 shows the transformation of an inverter schematic into its corresponding layout.

Each semiconductor technology has its own set of ground rules that a physical design has to com- ply with. The most important rules constrain the width of and the distance between polygons, and they have the primary impact on chip area. Each technology has its own recipe of how to implement physically the structures at the silicon surface, and, depending on the resolution, polygons which are

too close may melt together, and vice versa poly- gons which are too narrow may disappear com-

In semi-custom methodology layouts of cells and chips are to be seen under different aspects: cell layouts are crafted by semiconductor manufacturers and represent their intellectual property. Usually customers only receive the abstracts with a simpliﬁed layout containing only the outlines and the locations of the input and output terminals. The wires which interconnect the terminals are custom for the particular chip.

Design for Test

The topic test has not been recognized as part of an ASIC design for very long, and it is not mentioned within the Y chart. Designers were reluctant to spend effort on testing development, as that had not been considered a constructive step. However, test is key for quality of a chip and it is extremely critical because of high drop out rates typical for semiconductor manufacturing. Nowadays, the im- portance of test design and design for test is no longer doubted – in many cases a result of painful experience. It has been seen that:

• The cost of test grows faster than complexity (gate count) of a chip.
• Unless appropriate measures are taken during chip design, test of a state of the art ASIC can no longer be afforded both owing to the cost of test program development and recurring cost in production.

The answer to this crisis is design for test. This methodology requests the addition of circuitry that is of use only during production test. The additional elements provide access for the test equipment to the internal wires of the chip.

Apart from the design of the auxiliary test circuitry, test vectors are to be generated. These are a set of stimuli which will be applied to the circuit during test as well as the correct responses of the circuit.

The request for testability and the desired test method should also be part of the speciﬁcation, together with a target for test coverage.

Search This Blog

Electronic Design Automation (EDA)